AD9864: CLK & LO drive levels

Hello,

For a project I am currently working on we would like to drive the AD9864 LO and CLK ports directly. 

The clock generator which would generate the signals for this can output, amongst other options, LVDS and High Swing Differential Signalling (HSDS).

Based on my reading of the datasheet it seems that both the LO and CLK ports require a 0.3 V signal, so that they could be driven with an AC-coupled LVDS signal?

Or, if LVDS doesn't provide enough margin, HSDS could be used instead.

My questions then are these:

1. Is my understanding correct that the CLK port only requires 0.3V?

2. Would an AC-coupled LVDS/HSDS signal be appropriate to drive the LO and CLK ports?

Many thanks in advance,

Wouter