Hi,
The datasheet says AD9640 supports LVDS clocking and even gives an example of this.
However, the Table 5, row 1 specifies differential clock input levels as
High input level: 1.2V(min) to 3.6V(max)
Low input level: 0V(min) to 0.8V(max)
These levels don't appear consistent with LVDS?
Thanks
Joe
