AD9517-1 can not generated clock on all output channels

Hi all, 

We've dumped all registers of good board and bad boards for comparing, the only difference is the 0x01F register.

Good board: 0x01F = 0x4F

Bad boards: 0x01F = 0x0E

Regards,

Hi,

let's discuss the "good" board: The register 0x1F being equal to 0x4F indicates that:

-  bit 6 is 1, that is VCO calibration has finished

- bit 0 is 1, which shows the PLL is locked

- bit 5 is 0, which means the PLL is not in holdover, which makes sense if the PLL is locked

- bit 4 is 0, which means the PLL uses REF1 as reference

-bits 3,2,1 are 1, which mean that VCO, REF2 and REF1 are valid (I'm hoping bit 6 in register 0x1A is cleared to  0 for this statement to be true)

So the "good" chip functions with PLL locked from REF1 and produces outputs because the SYNC operation is done automatically after the VCO is calibrated.

On the "bad" board, the register 0x1F is 0xE, which means the VCO has not been calibrated (bit 6 is 0), the PLL is not in holdover (bit 5 is 0), which makes sense. If the VCO was not calibrated, the PLL cannot work at all, not even entering holdover.

So I believe you should execute a VCO calibration on the bad boards and then they should lock the PLL on REF1 and produce outputs function of REF1. See page 40 in revE data sheet for the VCO calibration procedure. Take a look how it is done for the first board and why that procedure is not replicated on the others. 

Petre