AD9689 multichip sync using timestamp

aim:in order to achieve two piece of AD9689's multichip sync using timestamp, I configurate AD9689 registers like follow:

(generally speaking, full bandwidth mode ; sysref N shot mode jesd204b  LMF=821 control bit CS2 CS1 )

SendCmdToAD9689(ADCSel, 0x003F, 0x80); //CHIP PDWN pin ignore
///Chip mode
SendCmdToAD9689(ADCSel,0x0200,0x00); //full bandwidth mode
SendCmdToAD9689(ADCSel,0x0201,0x00); //chip decimation ratio = 1
SendCmdToAD9689(ADCSel, 0x0120, 0x04); //N-shot mode;clk rising edge
SendCmdToAD9689(ADCSel, 0x0121, 0x00); //ignore 0 sysref
SendCmdToAD9689(ADCSel, 0x0122, 0x00); //SYSREF window

SendCmdToAD9689(ADCSel, 0x0571, 0x15); //JESD204B link power down
SendCmdToAD9689(ADCSel, 0x0572, 0x00); //CGS force
SendCmdToAD9689(ADCSel, 0x058B, 0x87); //scrambling off [7]=1, L = 8
SendCmdToAD9689(ADCSel, 0x058E, 0x01); //M = 2
SendCmdToAD9689(ADCSel, 0x058C, 0x00); //F = 1
SendCmdToAD9689(ADCSel, 0x058D, 0x13); //K = 20

SendCmdToAD9689(ADCSel, 0x01FF, 0x01); //timestamp mode
SendCmdToAD9689(ADCSel, 0x058F, 0x8D); //N=14 CS*2
SendCmdToAD9689(ADCSel, 0x0559, 0x50); //cs1 = 1
SendCmdToAD9689(ADCSel, 0x055A, 0x50); //cs2 = 1
SendCmdToAD9689(ADCSel, 0x056E, 0x00); //lane rate = 6.75-13.5Gb/s
//ADC test mode
SendCmdToAD9689(ADCSel, 0x0561, 0x00); //offset coding
SendCmdToAD9689(ADCSel, 0x0550, 0x0F); // 0x0F :ramp output

SendCmdToAD9689(ADCSel, 0x0571, 0x14); //JESD204B link power up


then I reset jesd204b ip core in FPGA , let HMC7044 generate a pluse of sysref, 100ns ,and jesd204b link set up, I received valid data. But I also received control bits signal at the same time.

it is why?

then I want to generate pluse of sysref again and add a timestamp into sample data, but I can not receive control bits signal.

And register 0X012A sysref counter is 0x0001 after I configurated ADC

Is there any wrong about my configuration? THANKS please.

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