Does AD9671 really support 4 channel/lane mode?

My development environment is AD9671-EBZ and ZC706.No matter how I set the AD9671 to be 4 channel/lane mode,the chip is always work in the default mode (2 channel/lane).

    Even when I set AD9671 register 0x021 to 0x22 (4 channels/ lane)and register 0x150 to 0x01(2lane/link),and readback value is the right value that I want to set.The chip's work mode changes nothing. FPGA jesd204 IP is sync done and receive data is 2 channels/lane.For example,gt_rx_p/n[0]-->AD9671 channel A and B.

I want to know if the AD9671 support 4 channel/lane mode.Or there is something need to be concerned when I initial the AD 9671,like the lane power down timing ,the lane power on timing ,register setting update timing and so on.

    Thanks very much for reply if you know something about that.

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    •  Analog Employees 
    on Apr 15, 2020 4:54 PM

    The AD9671 works in 4 ch/lane mode. Here is an example setup for 4 lane with 80 Msps. Compare it with your settings or share yours and we can review it.

     <Section Type="MACRO">
      <Name Parameter="Real Mode, 4 Lane, 80MHz, RF Dec ON"/>
      <PageName Parameter="Real Mode, 4 Lane, 80MHz, RF Dec ON"/>
      <Enable Parameter="False"/>
      <RunOnNewDUT Parameter="False"/>
      <UpdateCtrlrAfterExec Parameter="True"/>
      <Section Type="MACROCOMPONENTS">
       <Component Addr="0" Value="3C" R4Value="0" R5Value="0" WriteCommand="True"/>
       <Component Addr="2" Value="22" R4Value="0" R5Value="0" WriteCommand="True"/>
       <Component Addr="4" Value="0F" R4Value="0" R5Value="0" WriteCommand="True"/>
       <Component Addr="5" Value="3F" R4Value="0" R5Value="0" WriteCommand="True"/>
       <Component Addr="113" Value="27" R4Value="0" R5Value="0" WriteCommand="True"/>
       <Component Addr="11" Value="06" R4Value="0" R5Value="0" WriteCommand="True"/>
       <Component Addr="10C" Value="00" R4Value="0" R5Value="0" WriteCommand="True"/>
       <Component Addr="14" Value="00" R4Value="0" R5Value="0" WriteCommand="True"/>
       <Component Addr="8" Value="00" R4Value="0" R5Value="0" WriteCommand="True"/>
       <Component Addr="21" Value="19" R4Value="0" R5Value="0" WriteCommand="True"/>
       <Component Addr="199" Value="80" R4Value="0" R5Value="0" WriteCommand="True"/>
       <Component Addr="142" Value="04" R4Value="0" R5Value="0" WriteCommand="True"/>
       <Component Addr="188" Value="11" R4Value="0" R5Value="0" WriteCommand="True"/>
       <Component Addr="18B" Value="27" R4Value="0" R5Value="0" WriteCommand="True"/>
       <Component Addr="18C" Value="72" R4Value="0" R5Value="0" WriteCommand="True"/>
       <Component Addr="150" Value="03" R4Value="0" R5Value="0" WriteCommand="True"/>
       <Component Addr="182" Value="82" R4Value="0" R5Value="0" WriteCommand="True"/>
       <Component Addr="181" Value="01" R4Value="0" R5Value="0" WriteCommand="True"/>
       <Component Addr="10C" Value="20" R4Value="0" R5Value="0" WriteCommand="True"/>
       <Component Addr="F" Value="30" R4Value="0" R5Value="0" WriteCommand="True"/>
       <Component Addr="2B" Value="40" R4Value="0" R5Value="0" WriteCommand="True"/>
      </Section>
     </Section>

  • Hello , there is one problem with the configure to AD9671.When I set the register 0x188 to 0x11(enable the start code identifier),simple data on every lane  is always  0(rx_sync signal can be pulled up at this time).But if I set it to 0x00,there is sample data on the lane,even it is the default 4 lane mode. And  the sample data is not the 2lane mode that I want to set.I don't know why it happened.It feels like aligning the data on all lane is not correct.And it led to that sample data replacing is not working correctly.

  • Hi, do yo solve it ? I have the same problem with you ,could you help me if you solved it?Thank you

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