My development environment is AD9671-EBZ and ZC706.No matter how I set the AD9671 to be 4 channel/lane mode,the chip is always work in the default mode (2 channel/lane).
Even when I set AD9671 register 0x021 to 0x22 (4 channels/ lane)and register 0x150 to 0x01(2lane/link),and readback value is the right value that I want to set.The chip's work mode changes nothing. FPGA jesd204 IP is sync done and receive data is 2 channels/lane.For example,gt_rx_p/n-->AD9671 channel A and B.
I want to know if the AD9671 support 4 channel/lane mode.Or there is something need to be concerned when I initial the AD 9671,like the lane power down timing ,the lane power on timing ,register setting update timing and so on.
Thanks very much for reply if you know something about that.