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Clarification of RESET bit behavior for LTC2185 under read operation.

Page 28, Table 3 of the LTC2185 datasheet (rev 218543f) describes the operation of the RESET bit (A0[7]).

1 = Software Reset. All Mode Control Registers Are Reset to 00h. The ADC Is Momentarily Placed in SLEEP Mode. This Bit Is
Automatically Set Back to Zero After the Reset Is Complete

I interpret this to mean that the device reset operation is initiated by writing a 1 to A0[7] and that during the reset process, reading this bit will return a 1 until the reset cycle is complete. Whereupon reading A0[7] will return 0.

I observe, in practice, this to be incorrect.

Reading A0 returns 0xFF under all circumstances, before, during, and after the reset operation.

Can you please confirm that this description in Table 3 is misleading?

I believe that the text is trying to tell the engineer that they are not responsible for writing 0 to A0[7]. Yet it implies that one can monitor the reset process by reading A0[7].