AD9257 ADC Data Capture IP needed

Hi there,

For our application, we planned to use the AD9257 ADC on our custom RF board which is interfacing a FPGA board. I am wondering if there is any hdl reference design available like there is for AD9361? I would really appreciate if you can share the latest VHDL source code for capturing the LVDS data on a FPGA.

Thanks,

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    •  Analog Employees 
    on Mar 24, 2020 2:07 AM in reply to gensysco

    Hi, the FPGA code is designed to demonstrate the AD9257 in its default mode (14-bits). The chip does support dynamic reconfiguration, but the evaluation board HDL doesnt support it. you can take a look at the AD9637 datasheet to understand the data framing, and then apply it to the HDL you downloaded from the links above. This should enable you to have a HDL environment that supports both 12-bit and 14-bit modes. 

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