According the Table 33/34/35 in datasheet ,in the Full bandwidth mode (DCM = 1,the DDC are bypassed) the parameter N(N is the virtual converter resolution (in bits)),can be config from 8 to 16;But the ADC resolution is 14 BIT,My question is that ,what is the data structure of frame ,when the N =16,or N = 14? Is it explained in the datasheet?The parameter configed in the AD as follow picture.Looking forward to your reply! Thanks a lot!
see rev0 datasheet page 76 and 77. you should be able to derive the setup from the examples. the clock frequency you are providing is outside of the supported clock range. this range is also in the datasheet.
Hi UmeshJ: I solved the problem.Thanks!