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AD9629 input clock design


I have got a working design with 4 ADCs (AD9629), they have for each an input clock design just like the picture attached.

(I would like to keep 4 times AD9629 for versatility...)

All of my ADC are synchonized to the same clock at 5Mghz.

My question are:

- Is there enough (current/power) for powering 4 Adcs with a single clock differential input?

- Is there any precautions I need to implement?

thanks in advance.