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AD9629 Read

Thread Summary

The user is implementing AD9629 capture with an FPGA and facing issues with negative differential input voltages, where the ADC output appears offset by 2^11. The final answer suggests checking the FPGA design for unintentional offsets and experimenting with DCO-to-Data timing adjustments. The user confirms SPI communication and has tried changing the timing without success. The AD9629 datasheet and integrated logic analyzer were used for troubleshooting.
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Hi,

I am new to reading ADC. I want to use AD9629 in my design. And i want to read this with FPGA. How can i handle it? Where should i start when writing the VHDL code? What are the things i should be aware of?

Best regards.