I am new to reading ADC. I want to use AD9629 in my design. And i want to read this with FPGA. How can i handle it? Where should i start when writing the VHDL code? What are the things i should be aware of?
In offset binary mode and second condition(Vin+ - Vin- = -1V), i am reading 800H. I check the DFS pin and it is logic zero. So the output mode of ADC is offset binary. But it gave an output according to the 2's comp. mode in second condition. What can be the problem?
I am sending some values that i saved.
Vin+ - Vin- ADC Output
According to my results, the ADC does not work properly when the Vin+ - Vin- value goes to negative.
And also my DCO signal is not exactly a square wave, it is a sinusoidal wave. Could this be the source of the problem?
I agree that your output codes for positive differential input voltages look good.
Your output data for negative input voltages seems to have the same slope (ADC gain) as the output codes for positive values. Also, the data point you provided earlier with 0.46V - 1.34V = -0.88V falls almost on the same line. It is like you are adding an offset to your output codes when the MSB = 0.
Could you double check your FPGA design? Is it possible you are adding an unintentional offset of 2^11 to the codes for when the MSB = 0? When I subtract 2^11 from your output values when MSB = 0 (for negative differential analog input voltage), your output codes vs. input voltage all fall on a straight line.
If the values you get are consistent, I do not suspect it is a DCO issue. If you had SPI communication with AD9629 you could try changing DCO-to-Data timing as an experiment, but it sounds like you do not have SPI control. Can you change the capture timing in your FPGA?
Also, how did you observe the outputs directly at the ADC outputs?
I have SPI communication.So i can change DCO to data timing. Change capture timing means divide the clock, am i right?
I observed the outputs directly with Integrated Logic Analyzer.It is a Xilinx tool. I can observe the ADC output before the values entering the FPGA code.
No, I'm not referring to the clock frequency divider. Register 0x17 allows you to change the timing of DCO related to Data. For example, if you wanted to delay data with respect to the DCO you could do something like:
Write Register 0x17 = 001000100 #delay data by about 2.8ns
Write Register 0xFF = 0x01 #transfer bit to put previous register writes into effect
Please see the datasheet for more information.
Can you change capture timing in your FPGA?
You should have seen some difference in your captured data when you changed the DCO-data timing. Did you see any change? How many different values did you try?
Earlier in this thread you wrote that CSB is connected to DRVDD, which is why I thought you did not have SPI communication. Is CSB now being driven by a SPI controller of some sort?
I'm sorry but at this moment I do not have more ideas for you to try. As an ad hoc solution you might have to subtract 2^11 from your result when MSB = 0.