AD9629 Read

Hi,

I am new to reading ADC. I want to use AD9629 in my design. And i want to read this with FPGA. How can i handle it? Where should i start when writing the VHDL code? What are the things i should be aware of?

Best regards.

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  • 0
    •  Analog Employees 
    on Feb 12, 2020 1:05 AM

    Hi,

    The sample FPGA code has been sent. I hope this gets you going.

    Take care.

    Doug

  • Hi, 

    I want to ask another question. Is it possible to do these operations with microblaze processor and IP cores?

    Best regards.

  • 0
    •  Analog Employees 
    on May 8, 2020 2:19 AM in reply to hrnttk

    Hi Harun,

    I agree that your output codes for positive differential input voltages look good.

    Your output data for negative input voltages seems to have the same slope (ADC gain) as the output codes for positive values. Also, the data point you provided earlier with 0.46V - 1.34V = -0.88V falls almost on the same line. It is like you are adding an offset to your output codes when the MSB = 0.

    Could you double check your FPGA design? Is it possible you are adding an unintentional offset of 2^11 to the codes for when the MSB = 0? When I subtract 2^11 from your output values when MSB = 0 (for negative differential analog input voltage), your output codes vs. input voltage all fall on a straight line.

    Thank you.

    Doug

  • Hi Doug,

    I checked my FPGA code and there is no an unintentional offset. And also i checked the output signals directly from the ADC parallel channels(no processing). The results is still the same.

    Thank you.

    Harun

  • 0
    •  Analog Employees 
    on May 19, 2020 4:18 PM in reply to hrnttk

    Hi Harun,

    If the values you get are consistent, I do not suspect it is a DCO issue. If you had SPI communication with AD9629 you could try changing DCO-to-Data timing as an experiment, but it sounds like you do not have SPI control. Can you change the capture timing in your FPGA?

    Also, how did you observe the outputs directly at the ADC outputs?

    Thanks,

    Doug

  • Hi Doug,

    I have SPI communication.So i can change DCO to data timing. Change capture timing means divide the clock, am i right? 

    I observed the outputs directly with Integrated Logic Analyzer.It is a Xilinx tool. I can observe the ADC output before the values entering the FPGA code.

    Thank you.

    Harun

  • 0
    •  Analog Employees 
    on May 20, 2020 3:15 PM in reply to hrnttk

    Hi Harun,

    No, I'm not referring to the clock frequency divider. Register 0x17 allows you to change the timing of DCO related to Data. For example, if you wanted to delay data with respect to the DCO you could do something like:

    Write Register 0x17 = 001000100 #delay data by about 2.8ns
    Write Register 0xFF = 0x01 #transfer bit to put previous register writes into effect

    Please see the datasheet for more information.

    Can you change capture timing in your FPGA?

    Thank you.

    Doug

Reply
  • 0
    •  Analog Employees 
    on May 20, 2020 3:15 PM in reply to hrnttk

    Hi Harun,

    No, I'm not referring to the clock frequency divider. Register 0x17 allows you to change the timing of DCO related to Data. For example, if you wanted to delay data with respect to the DCO you could do something like:

    Write Register 0x17 = 001000100 #delay data by about 2.8ns
    Write Register 0xFF = 0x01 #transfer bit to put previous register writes into effect

    Please see the datasheet for more information.

    Can you change capture timing in your FPGA?

    Thank you.

    Doug

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