AD9629 Read

Hi,

I am new to reading ADC. I want to use AD9629 in my design. And i want to read this with FPGA. How can i handle it? Where should i start when writing the VHDL code? What are the things i should be aware of?

Best regards.

Parents
  • 0
    •  Analog Employees 
    on Feb 12, 2020 1:05 AM

    Hi,

    The sample FPGA code has been sent. I hope this gets you going.

    Take care.

    Doug

  • Hi, 

    I want to ask another question. Is it possible to do these operations with microblaze processor and IP cores?

    Best regards.

  • 0
    •  Analog Employees 
    on Apr 28, 2020 1:44 AM in reply to hrnttk

    Hi HrnTtk,

    To verify you capture the ADC outputs properly, I recommend that you use the output test patterns controlled by Register 0x0D Bits[3:0]. For example, to output a checkerboard pattern you would do the following SPI writes:

    Write Register 0x0D = 0x04
    Write Register 0xFF = 0x01

    This will put AD9629 in output checkerboard test mode. There are several other test patterns to choose from. Please see Table 16 in the AD9629 datasheet for more options.

    Table 12 in the AD9629 datasheet shows the output values for a few selected voltage values at the analog input. I numbered them in the picture above to match the numbers in the description below.

    1. This shows the value when the differential voltage at the ADC inputs are less than the negative full scale value. This means that the VIN+ - VIN- is less than 1V by more than 0.5LSB. The output is a minimum code and the MODE/OR pin goes high, if the MODE/OR pin is in OR mode.
    2. This is when the differential input voltage is right at the negative full-scale value (VIN+ - VIN- = 1V). The ADC outputs the minimum code. OR does not go high.
    3. This is with VIN+ = VIN-. When the voltage on each input are equal to each other, the differential input voltage is zero. In this case the ADC outputs a mid-scale code.
    4. This is with the differential input voltage at full-scale. The ADC outputs a maximum code value.
    5. This is with the differential input voltage above full-scale. The ADC outputs a maximum code value and the OR pin goes high, if the MODE/OR pin is in OR mode.

    Does this answer your question?

    Thank you.

    Doug

  • Hi Doug,

    In offset binary mode and second condition(Vin+ - Vin- = -1V), i am reading 800H. I check the DFS pin and it is logic zero. So the output mode of ADC is offset binary. But it gave an output according to the 2's comp. mode in second condition. What can be the problem?

    Best regards.

    Harun

  • 0
    •  Analog Employees 
    on May 5, 2020 7:16 PM in reply to hrnttk

    Hi Harun,

    Is your CSB pin connected to DRVDD to put the AD9629 in "pin mode" (non-SPI mode)?

    Thank you.

    Doug

  • Yes, my CSB pin connected to DRVDD.

    Thank you.

  • Hi Doug,

    I am sending some values that i saved.

    Vin+ - Vin-              ADC Output

    -1V                              800

    -0.28V                         DA9

    0V                               807

    0.32V                          AB4

    0.68V                          D75

    1V                               FFF

    According to my results, the ADC does not work properly when the Vin+ - Vin- value goes to negative. 

    And also my DCO signal is not exactly a square wave, it is a sinusoidal wave. Could this be the source of the problem?

    Thanks.

Reply
  • Hi Doug,

    I am sending some values that i saved.

    Vin+ - Vin-              ADC Output

    -1V                              800

    -0.28V                         DA9

    0V                               807

    0.32V                          AB4

    0.68V                          D75

    1V                               FFF

    According to my results, the ADC does not work properly when the Vin+ - Vin- value goes to negative. 

    And also my DCO signal is not exactly a square wave, it is a sinusoidal wave. Could this be the source of the problem?

    Thanks.

Children
  • 0
    •  Analog Employees 
    on May 8, 2020 2:19 AM in reply to hrnttk

    Hi Harun,

    I agree that your output codes for positive differential input voltages look good.

    Your output data for negative input voltages seems to have the same slope (ADC gain) as the output codes for positive values. Also, the data point you provided earlier with 0.46V - 1.34V = -0.88V falls almost on the same line. It is like you are adding an offset to your output codes when the MSB = 0.

    Could you double check your FPGA design? Is it possible you are adding an unintentional offset of 2^11 to the codes for when the MSB = 0? When I subtract 2^11 from your output values when MSB = 0 (for negative differential analog input voltage), your output codes vs. input voltage all fall on a straight line.

    Thank you.

    Doug

  • Hi Doug,

    I checked my FPGA code and there is no an unintentional offset. And also i checked the output signals directly from the ADC parallel channels(no processing). The results is still the same.

    Thank you.

    Harun

  • 0
    •  Analog Employees 
    on May 19, 2020 4:18 PM in reply to hrnttk

    Hi Harun,

    If the values you get are consistent, I do not suspect it is a DCO issue. If you had SPI communication with AD9629 you could try changing DCO-to-Data timing as an experiment, but it sounds like you do not have SPI control. Can you change the capture timing in your FPGA?

    Also, how did you observe the outputs directly at the ADC outputs?

    Thanks,

    Doug

  • Hi Doug,

    I have SPI communication.So i can change DCO to data timing. Change capture timing means divide the clock, am i right? 

    I observed the outputs directly with Integrated Logic Analyzer.It is a Xilinx tool. I can observe the ADC output before the values entering the FPGA code.

    Thank you.

    Harun

  • 0
    •  Analog Employees 
    on May 20, 2020 3:15 PM in reply to hrnttk

    Hi Harun,

    No, I'm not referring to the clock frequency divider. Register 0x17 allows you to change the timing of DCO related to Data. For example, if you wanted to delay data with respect to the DCO you could do something like:

    Write Register 0x17 = 001000100 #delay data by about 2.8ns
    Write Register 0xFF = 0x01 #transfer bit to put previous register writes into effect

    Please see the datasheet for more information.

    Can you change capture timing in your FPGA?

    Thank you.

    Doug