I am new to reading ADC. I want to use AD9629 in my design. And i want to read this with FPGA. How can i handle it? Where should i start when writing the VHDL code? What are the things i should be aware of?
Thank you very much for your help. I had an opportunity to review the code right now. I have some questions about the code.
1. You wrote the code for AD9649. This is a 14 bit resolution ADC. But the data input of the code is 15 bit. What is the reason of this? And what is the function of ADC_MAX_DATA_SIZE(16 bit)?
2. Did you monitor the output data via USB? Am i right?
I am not the author of the FPGA code, so I do not know the details or specifics. I can provide some guesses.
I do not know the function of ADC_MAX_DATA_SIZE(16 bit). From the sound of it, maybe it is setting the maximum limit of the code to capture 16 bit outputs.
I'm sorry but I do not know the capability of the MicroBlaze compared to the Virtex4 on the HSC-ADC-EVALCZ for AD9629 capture.
I can ask one of our FPGA developers for their opinion on this, but of course we cannot guarantee any capability, compatibility or result.
I am trying to read AD9629 and i want to ask some questions.
This is my circuit. Analog input range(Pin-9) of AD8475 is 0 to 4.2V. ADC inputs become 0.46V and 1.34V when AD8475 input is 0.29. And digital output of the ADC is 8D5. This value is true?
What should be the relationship between input values and output?
I can't understand this table. What is the meaning of this?
Thanks for help.
To verify you capture the ADC outputs properly, I recommend that you use the output test patterns controlled by Register 0x0D Bits[3:0]. For example, to output a checkerboard pattern you would do the following SPI writes:
Write Register 0x0D = 0x04
Write Register 0xFF = 0x01
This will put AD9629 in output checkerboard test mode. There are several other test patterns to choose from. Please see Table 16 in the AD9629 datasheet for more options.
Table 12 in the AD9629 datasheet shows the output values for a few selected voltage values at the analog input. I numbered them in the picture above to match the numbers in the description below.
Does this answer your question?
In offset binary mode and second condition(Vin+ - Vin- = -1V), i am reading 800H. I check the DFS pin and it is logic zero. So the output mode of ADC is offset binary. But it gave an output according to the 2's comp. mode in second condition. What can be the problem?