When I write 0x06 to 0x0110, 0x6E to 0x0111, 0x64 to 0x0112 only for channel B, which means totally delay 200 ps for channel B than channel A. And I set ADC test mode(ramp out). The result is that when I set channel delay, channel A (M0) sample points are 12771 12772 12773 ........ . and channel B (M1) sample points are 12773 12774 12775.......... M1 is 2 sample points delay than M0.But when I do not set channel delay, channel A and channel B sample points are the same, 12771,12772,12773...... for example.
P.S. refclk is 312.5MHz, and Lane = 8
What is the end application? what is the adc use case? what is the motivation for doing this test?
Thanks, sir. I want to use AD9689 to achieve 5Gsps sample system. Can it be realized by AD9689? Because I think the ADC supports superfine delay and can delay sample clock for 200ps.
achieve 5Gsps by Time-Interleaving using a piece of AD9689.