AD9633 and zynq fpga connection

If the layer voltage of fpga is set to 2.5v, and the interface protocol is set to lvds25 in vivado, the voltage of AD9633 is 1.8v, and the multiple groups of LVDS of AD can be directly connected to the difference line of the bank, is there any problem?

  • 0
    •  Analog Employees 
    on Jan 8, 2020 5:40 PM

    Hi Xmarcus724,

    I do not know about Zynq, but the AD9633-to-FPGA interface works well when I have the FPGA IO voltage set to 2.5V on the HSC-ADC-EVALCZ capture board (Xilinx Virtex4).

    I believe lvds25 works with the AD9633 outputs, but please verify the levels requirements with the AD9633 output levels as specified in the datasheet.

    Thank you.

    Doug