We reference the front end design of CN0252 on AD9613 circuits. But it is found that input clock superimposed on the analog signal at the ADC input. Based on sampling results, the superposition signal will affect the sampling accuracy (from gain 0.511 to 0.53). At the same time, use eval-ad9613 evaluation board to check this problem, with j506 input 250MHz sampling clock; also can reproduce the phenomenon,.
1. How to explain this phenomenon?
2. Is there a programme to eliminate the impact or improve the test accuracy?