Eval-ad9613 sampling clock superimposed on the analog input signal

We reference the front end design of CN0252 on AD9613 circuits. But it is found that input clock superimposed on the analog signal at the ADC input. Based on sampling results, the superposition signal will affect the sampling accuracy (from gain 0.511 to 0.53). At the same time, use eval-ad9613 evaluation board to check this problem, with j506 input 250MHz sampling clock; also can reproduce the phenomenon,.


1. How to explain this phenomenon?
2. Is there a programme to eliminate the impact or improve the test accuracy?

thx~

Best regards,

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  • 0
    •  Analog Employees 
    on Feb 5, 2020 8:16 PM

    Hi,

    The Analog input characteristics are not identical between your AD9265 CN0252 reference design and the AD9613, so some tweaks to the input matching network may be necessary to optimize performance. Also its not clear from your picture that the configuration/placement of the Amp/ADC/FPGA brds are optimal to prevent parasitic coupling between the sampling Clock and Analog Input signal paths? Are you using appropriate external filtering on your CLK and Ain signal sources? Please refer to AN-835 for recommendations on best ADC testing practices.

    Best Regards,

    TonyM

Reply
  • 0
    •  Analog Employees 
    on Feb 5, 2020 8:16 PM

    Hi,

    The Analog input characteristics are not identical between your AD9265 CN0252 reference design and the AD9613, so some tweaks to the input matching network may be necessary to optimize performance. Also its not clear from your picture that the configuration/placement of the Amp/ADC/FPGA brds are optimal to prevent parasitic coupling between the sampling Clock and Analog Input signal paths? Are you using appropriate external filtering on your CLK and Ain signal sources? Please refer to AN-835 for recommendations on best ADC testing practices.

    Best Regards,

    TonyM

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