We bought a DC1525A-L. I'm trying to configure it via SPI interface for a week, but I can not get MOSI outputs properly from your Eval Board.
Firstly, I proved my pinout mappings by using Vivado ILA hardware Debug window.
Then We probed FMC outputs(looks fine)
Then We probed DC1525A-L with an oscilloscope and saw there is no SPI clock coming.
After that we traced your schematic and found a production failure about SPI clock. Then we fixed the problem(I took photos before fixing and after fix)
After fix, we can get SPI clock and I can configure my adc properly. I can always see my FPGA's MOSI(ADC's MISO), SS and SPI Clock signals properly.
But I can not see ADC's MOSI output, only whenever I reset ADC, I can see some output from MOSI or If I send all 16bits as 0xFF 0xFF I can see 0xFF 0xFF as MOSI output(just for trying).
I can set Register2 as 12bits 1Lane mode or 2 Lanes mode:
But I can not get register2's value:
I'm using ZC702 and using Xilinx's SPI driver on Embedded Linux. I'm adding also Vivado Block design view:
Thanks in advance.
We don't recommend using a clock from an FPGA since there will be jitter and noise on that clock. Jitter and noise will cause the ADC performance to degrade. We recommend using a clock with less than…
It was my fault.
I tried ZYNQ’s other input port(SPI0_MISO_I). Before I was using SPI0_MISO_O port of ZYNQ.
Actually, when we test it before, we can see after Reset there were some bits…
What are your jumpers set to?
All of jumpers are at default positions. You can look also it's photo.
I feed 5V power and external clock to bring up setup.
How can I supply a proper clock to DC1525A-L without using an extra signal generator.
When I connect an external clock to DC1525A-L's CLK+ port, I can see 4 channels properly, but I do not want to use an extra signal source.
I m using ZC702 and I tried to generate clock for DC1525A-L in FPGA logic.
I tried ZYNQ7's processor7 FCLK_CLK1, clock_wizard and my custom counter based clock divider hdl code.
None of them worked properly with DC1525A-L. I connect also this signals to Oscilloscope and they seems not good. I'm getting clocks from PMOD2 GPIO of ZC702 with an SMA cable.
Maybe problem is cable, maybe I m doing something wrong.
We don't recommend using a clock from an FPGA since there will be jitter and noise on that clock. Jitter and noise will cause the ADC performance to degrade. We recommend using a clock with less than 200fs of jitter, FPGAs can have 10-100ps of jitter.
Thank you so much.
It is wonderful to know, what is vendor's recommendation. Issue is closed.
About SPI - MOSI problem , I wait for your reply.