LTC2313-12 SPI issue

I am using an LTC2313-12 in combination with an ESP32 using (V)SPI functionality of the ESP32.  

According to the description in the datasheet (https://www.analog.com/media/en/technical-documentation/data-sheets/231312fb.pdf -- p10/22 - Serial Interface) and the graph (p11/22 - Timing diagram), the MSB should be available on first SCK falling edge.

When sending 2 bytes (2 x 8 bits) via SPI, I can measure that the SCK line sends 2 x 8 pulses to the LTC2313-12, while the CONV is LOW.  Looking at the SDO line at the same moment, it is noticed that the MSB appears at the second SCK falling edge and not, as noted in the datasheet, with the first SCK falling edge.  The LSB than coincides with the 14Th SCK pulse = 6Th pulse of the second byte).

I can resolve this by taking the last 6 bits of the MSbyte and attach to this MSbyte the first 6 bits of the LSbyte (Result = MSbyte <<6 | LSbyte >>2.  This gives me the required result over the complete range (obtaining a high speed 0000 - 4096 output for 0.0V to 2.048V input), but it feels wrong that the result is not as predicted by the datasheet.

Changing SPI divider 2x, 4x, 8x, ... does not change the result.

Is the datasheet wrong, or am I doing something wrong ?  

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    These are measurements are done in a test environment on a prototype circuit.  Ground plane is not available/optimized in this test environment, so I expected noisy signalling already from the beginning.  The prototyping circuitry works as expected with the only exemption that the timing is not as espected (subject of this issue message(s).  However, by shifting SDO x bytes at readout, I obtain the desired result.  If in this prototype test environment it could indeed be that the length of the SCK, SDO and CONV lines (all three about 6cm long) including non optimized grounding is/was the reason for this 2 bytes shift (which I cannot explain however), I can always resolve this requirement for x shift in the software.  The final PCB's are currently in production, so I could not yet provide you at this moment measurements, made in this final configuration. In the final solution, the ground plane, as well as SMD, low ESR capacitors will be used and the SCK, SDO and CONV lines are respectively 6.9, 8.1 and 3.8 mm long.  I am convinced that the quality of the signals will be much better in this environment.  The reason of my concern, expressed in this message(s) is, is that the 2 byte shift should to my opinion not have occured, not even in the test environment.  Leave this up to your opinion of course.

    Thanks anyway for making the effort in having this cleared up.  I am curious ...

    By the way, the LTC231x family of ADC's are great !  Small size, high performance and only few peripheral components required.  I will certainly use them in other projects.

  • 0
    •  Analog Employees 
    on Dec 20, 2019 3:13 PM in reply to Yves Delbrassine

    The ringing on the digital lines can cause the LTC2313 to not properly clock out the data. The data sheet waveforms are correct. When you get your PCB, if you are still having problems I will be better able to assist you.