LTC2313-12 SPI issue

I am using an LTC2313-12 in combination with an ESP32 using (V)SPI functionality of the ESP32.  

According to the description in the datasheet (https://www.analog.com/media/en/technical-documentation/data-sheets/231312fb.pdf -- p10/22 - Serial Interface) and the graph (p11/22 - Timing diagram), the MSB should be available on first SCK falling edge.

When sending 2 bytes (2 x 8 bits) via SPI, I can measure that the SCK line sends 2 x 8 pulses to the LTC2313-12, while the CONV is LOW.  Looking at the SDO line at the same moment, it is noticed that the MSB appears at the second SCK falling edge and not, as noted in the datasheet, with the first SCK falling edge.  The LSB than coincides with the 14Th SCK pulse = 6Th pulse of the second byte).

I can resolve this by taking the last 6 bits of the MSbyte and attach to this MSbyte the first 6 bits of the LSbyte (Result = MSbyte <<6 | LSbyte >>2.  This gives me the required result over the complete range (obtaining a high speed 0000 - 4096 output for 0.0V to 2.048V input), but it feels wrong that the result is not as predicted by the datasheet.

Changing SPI divider 2x, 4x, 8x, ... does not change the result.

Is the datasheet wrong, or am I doing something wrong ?  

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  • 0
    •  Analog Employees 
    on Dec 2, 2019 4:31 PM

    Hi Yves,

    The data sheet says that the MSB is shifted out 10ns after the falling edge of CONV. If you are starting with SCK high, and the first falling edge occurs before SDO is active, then yes the second falling edge of SDO would capture the MSB as shown in Figure 6 of the LTC2313-12 data sheet.

    The LTC2313-12 shifts data out on each falling edge of SCK. The previous data remains valid for at least 1ns after the falling edge. If SCK is less than 54MHz you could use the rising edge of SCK to capture SDO. This would limit the maximum sample rate to 1.8Msps.

  • Hello Ghoover, thank you for this clarification, though, I am starting with SCK LOW. 

    As mentioned, I am communicating with the LTC2323-12 wit an ESP32 at SPI clock divided by 2.

    The complete conversion and readout Cycle is intiated by bringing SDO LOW for about 200ns, than bring it HIGH for about 300ns (datasheet tells me it must be minimal 247ns) to achieve conversion, followed by a LOW to perform readout. When 'firing 2 consecutive SPI transmission requests more than 100ns after this CONV LOW, I observe that the SCK line starts going HIGH for 2 x an 8 pulse train (SCK period is about 127ns).  The MSB however is shifted out on the SDO (MISO) pin on the second SCK falling edge.

    When I am using SPI clock NON divided, I notice that the conversion is not stable, but also that the MSB is than starting shifting out on the 3rd SCK falling edge.  I did not measure extensively on this NON divided SPI, since the SPI bus in my design is used for other purposes as well (SPI TFT display), which only works fine on SPI divided by 2.

    What I also have to mention is that all above measurements were performed on a 'test PCB' which was not the best condition to test on higher frequencies, since SCK, CONV and SDO lines were not optimized to the high speeds.  

    Anyway, for me the LTC functions OK and provides reliable conversions for my purpose.  Even if I know that MSB is shifted out on second falling edge of SCK, I can solve this via the software.  The real PCB for my circuit is now under production.  This PCB does take into account design considerations for higher SCK, CONV and SDO rates.  I am curious to see if this was really an "test set-up" issue or ont and will then revert on it.

    Thanks anyway for your answer, and if by reading the above you could point my attention on something I did not consider well, feel free to react.  Answer will very much be appreciated.

  • 0
    •  Analog Employees 
    on Dec 9, 2019 2:51 PM in reply to Yves Delbrassine

    Hi Yves,

    Can you provide an oscilloscope photo showing CONV, SCK and SDO? This will make it a lot easier for me to comment about what you are seeing.

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  • PDF

    Dear Ghoover, sorry for the delay in answer, but I had to re-buid my test setup in order to provide and document the requested measurement results.  Please find hereby in attachment the different timings for SDO, SCK and CONV.  Measurement was done with 10Mhz SPI speed, due to restrictions by length of the lines in the test-setup.  I noticed that, when using higher frequencies (SPI on 40MHz) the SDO MSB is transmitted on SCK 3 and LSB on SCK 15 falling edge.

  • 0
    •  Analog Employees 
    on Dec 19, 2019 6:04 PM in reply to Yves Delbrassine

    There is a lot of ringing on the photos. Is your circuit built on a PCB with a solid ground plane and proper bypassing? Another possibility is that the ground lead of your oscilloscope is very long. Can you provide a single photo showing showing the entire data read cycle with SDO, SCK and CONV?

  • PDF

    These are measurements are done in a test environment on a prototype circuit.  Ground plane is not available/optimized in this test environment, so I expected noisy signalling already from the beginning.  The prototyping circuitry works as expected with the only exemption that the timing is not as espected (subject of this issue message(s).  However, by shifting SDO x bytes at readout, I obtain the desired result.  If in this prototype test environment it could indeed be that the length of the SCK, SDO and CONV lines (all three about 6cm long) including non optimized grounding is/was the reason for this 2 bytes shift (which I cannot explain however), I can always resolve this requirement for x shift in the software.  The final PCB's are currently in production, so I could not yet provide you at this moment measurements, made in this final configuration. In the final solution, the ground plane, as well as SMD, low ESR capacitors will be used and the SCK, SDO and CONV lines are respectively 6.9, 8.1 and 3.8 mm long.  I am convinced that the quality of the signals will be much better in this environment.  The reason of my concern, expressed in this message(s) is, is that the 2 byte shift should to my opinion not have occured, not even in the test environment.  Leave this up to your opinion of course.

    Thanks anyway for making the effort in having this cleared up.  I am curious ...

    By the way, the LTC231x family of ADC's are great !  Small size, high performance and only few peripheral components required.  I will certainly use them in other projects.

  • 0
    •  Analog Employees 
    on Dec 20, 2019 3:13 PM in reply to Yves Delbrassine

    The ringing on the digital lines can cause the LTC2313 to not properly clock out the data. The data sheet waveforms are correct. When you get your PCB, if you are still having problems I will be better able to assist you.