Hi, I'm capturing data with AD9208-3000EBZ and a custom FPGA receiver board. The problem is that I see abrupt changes in captured signal level.
The AD9208 configuration is:
1. Sample rate is 3GSps.
2. 1 DDC enabled, real input (only from channel A), complex output, decimate by 4.
3. DDC's NCO in ZIF mode.
4. JESD is set to operate in Subclass 0 mode. (L, M, F) = [2, 2, 2], N=16, N'=16. Resulting lane rate is 15Gbps.
I use 10MHz signal as an AD9208 input.
This is how captured data looks like:
But when I enable various test modes, I see no such jumps.
Ramp test mode output (reg 0x0550 = 0x0F, reg 0x0327 = 0x05):
1/0-word toggle test mode output (reg 0x0550 = 0x07, reg 0x0327 = 0x05):
Output when NCO IF = 10MHz with enabled test mode:
What can be the reason of this? I tested two signal generators as input sources and this problem exists in both cases.
Well, I have found the solution myself. The problem was a software bug that enabled dc coupling instead of ac.
I am glad you were able to get it fixed.