I'm trying to configure the ADC9680-1000, for using 4 DDCs. The idea is to split the input band (from -fs/2 to fs/2 in 4, 1 per DDC channel: from -500 to -250, from -250 to 0, from 0 to 250 and finally from 250 to 500) so I will have an effective output sampling frequency of 250 Msps for internal processing in the FPGA (required).
As far as I understand, I should set the Fc of each DDC (NCO_FTW) and configure the ADC as follows:
With this configuration I spect to receive in the JESD rx_data word (128 bits), from LSB to MSB: [I_DDC0, Q_DDC0, I_DDC3, Q_DDC3, I_DDC1, Q_DDC1, I_DDC2, Q_DDC2] (I checked this distribution using the tests modes).
The JESD links are ok.
This image corresponds to an input signal of 20 MHz (Just in the channel A of the board, so I spect to read it in the I channels, of DDC0 and DDC2, as a 166,67 MHz - 20 MHz = 146,67 MHz signal), but what I'm seeing is not what I spected:
This second image corresponds to same configuration, but an input signal of 55 MHz in channel A (again, I spect to see it in DDC0 and DDC2):
Any idea of where I would be making a mistake in the configuration?. Any help will be appreciated.
Thanks in advance!
I solved it.
lferreyro, my understanding is that the AD-FMCDAQ2-EBZ software is setup to only support full bandwidth (DDC bypass) mode, in the fpga side. I think you will have to recompile the fpga setup to accommodate the DDC.
rgetz, can you please comment?
So, if it's helpfull for anybody, with this configuration you have 4 DDCs at 250 Msps as output. The mapping of the data is I wrote in original post.