I'm using the LTC2292 and am multiplexing both channels through channel A. The data channels connect to an FPGA for data processing. The timing diagram on page 14 makes it look like the FPGA should sample channel A data on the falling clock edge and channel B data on the rising clock edge, using the same clock as that used to drive the ADC. Is this correct? I'm clarifying because the only other example I could find was of a design (with the same setup) which samples channel A data on the rising edge and B on the falling edge. This engineer's designs are generally of good quality, which is why I'm second-guessing myself.
Thanks
