Do you have any Serial LVDS ADC Reference Design?

Hi again,

I asked a simple question, but there is no reply.

Do you have any Serial LVDS ADC Reference Design?

Thanks.

Verilogp2175_src.zip

Here you go. 

Hi @Clarence.Mayott,

Thanks a lot for your sharing. 

I examine it.

Saban

OK, let me know if you have any other questions. 

Hi Clarence.Mayott,

I'm exploring your design and also I read this document completely.

I have DEMO CIRCUIT 1525A-L(LTC2170 IUKG-12) evaluation board.

1. First question is about configuring ADC. How can I configure LTC2170-12 by using your design.
Is there any software that calls some commands to configure ADC.
Where can I find call functions sequence.
I know there is an application to configure LTC2175, but it works only with ADI's carrier board.
I want to bring up this ADC as soon as possible. I want to plan ILA to see retrieved LVDS data.
Can I use also VIO to configure ADC(by sending 16bits configuration word via SPI e.t.c.)

2. As my understanding, your code designed for 4 Channels, 8 LVDS lanes(every channel uses 2-lane)
I must use 1-lane mode for every 4 Channels(instead of 2-lane mode)
Is it possible to configure your design as it utilizes 1-lane mode scenario instead of 2-lane mode for LVDS communication.

3. Can I directly use your code to get 12 bits by enabling define LTC2175 line or I must get 16 bits and need to ignore 4 dummy bits?
Your design uses Xilinx's EXAMPLE_MGT design as base. (I do not need to store data, instead I want to transfer it from cheap Xilinx Chip to Xilinx Chip directly)
(I want to describe my understandings from your design.
Firstly It is configurable between LTC2195 and LTC2175(Current version is LTC2195, I need to enable this comented line//`define LTC2175)
LTC2195 has 16 bits and your design is written according to 16 bits, LTC2175 has 12 bits.
You are writing 72 bits into a Buffer). (4 Channels(16 bit)*4) + (4 Channels * 2) Channel definer constant.

4. Is there a constraint file. By using this file I can easily port constraints to ZC702. I do not know which pins I do not need to use.

Regards,

Saban

1.  The software is PScope and it will configure the ADC.  If you write your own FPGA code you will need to program the device yourself with a SPI interface.

2. Our code is written for 2 lane, but you can modify it for one lane as well.

3. If you rewrite the code you can use 12 bit alignment and collect data that way.

4.  I do not have a constraints file for the ZC702.

You might want to look at this article:  

https://www.xilinx.com/support/documentation/application_notes/xapp524-serial-lvds-adc-interface.pdf

It will be much more useful than talking to me

Hi Clarence.Mayott,

1. I know there is a software named PScope, but it is an exe, there is no source code so that I can port it according to our needs. It can run only for specific Carier board, but I need to run it with ZC702.

Before I used Analog Devices' iio osciloscope application as same purpose. I had source code and changed it acording to our needs.

Thanks you very much for your quick reply.

Regards,

Saban

There is linearlabtools if you want a way to talk to the DC1525 with python or another piece of software, that is similar to IIO scope.  It can be downloaded here:  

https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-platforms/linearlab-tools.html

There is linearlabtools if you want a way to talk to the DC1525 with python or another piece of software, that is similar to IIO scope.  It can be downloaded here:  

https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-platforms/linearlab-tools.html

Hi Clarence.Mayott,

Thank you for your sharing.

Now we can configure your ADC, but it had a production failure. I described in this link.

I can see ADC' MISO, CLK, SS, but I can not query registers over SPI. Because ADC's MOSI is not populating correct results.

Regards,

Saban

What are your jumpers set to?