ad9680 jesd204

Plsase help me  

First of all when I use the SPI interface to configure the ad9680, I find that the PLL lock status register 0x56f is set to 1 for a while, 0 for a while, and then 1 again. It will be repeated several times, although the last 1 is in a stable state. Is there any problem with my use? Is this normal.

 Secondly And my sync signal is often unlocked, that is, suddenly pulled down, sometimes repeatedly pulled up and down

The last,When I used the self-test mode of ad9680, the waveform came out was sawtooth wave, and the data transmission was good. However, when I used the external sampling, which was the normal mode, I found that the data she got through the FPGA was just a bunch of clutter. Could you please tell me what was wrong with me

Thanks for your help

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Top Replies

    •  Analog Employees 
    Apr 25, 2021 +1 verified
    PLL lock status register 0x56f is set to 1 for a while, 0 for a while, and then 1 again.

    this probably means your clock source is not stable. 

    Secondly And my sync signal is…
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