AD9656 dynamic level


We are using AD9656 evaluation board and we carry out the following test.

We configure the ADC register correctly with 2,8Vpp input span, quick configuration : One ADC per lane etc.

We put a sinus signal of 1MHz on the input A and check the digital value for different voltage Vpp values.

When we increase the voltage between 100mVpp and 2,5Vpp, from a certain value, we note that the digitalized result is lower than the expected result.
We see a compression of data at the end of the curve of data point instead of linear curve.

This is due to the track and hold part of ADC, because we have check the analog front-end and it's work well.

Can we have more information of track and hold structure?
What is the value of CPAR and CSAMPLE?
We want to make a simulation of this part with LTSpice, but we don't have information of how the ADC take the value of CSAMPLE (discharge of CSAMPLE complete, partial etc.).
Where the outputs of the ADC input structure is connected?

Thank you in advance for your answers.

Best regards,