AD9656 dynamic level


We are using AD9656 evaluation board and we carry out the following test.

We configure the ADC register correctly with 2,8Vpp input span, quick configuration : One ADC per lane etc.

We put a sinus signal of 1MHz on the input A and check the digital value for different voltage Vpp values.

When we increase the voltage between 100mVpp and 2,5Vpp, from a certain value, we note that the digitalized result is lower than the expected result.
We see a compression of data at the end of the curve of data point instead of linear curve.

This is due to the track and hold part of ADC, because we have check the analog front-end and it's work well.

Can we have more information of track and hold structure?
What is the value of CPAR and CSAMPLE?
We want to make a simulation of this part with LTSpice, but we don't have information of how the ADC take the value of CSAMPLE (discharge of CSAMPLE complete, partial etc.).
Where the outputs of the ADC input structure is connected?

Thank you in advance for your answers.

Best regards,

  • 0
    •  Analog Employees 
    on Nov 11, 2019 5:23 PM over 1 year ago

    Hi Daniel,

    Thank you for using the AD9656.

    Figure 46 is a very simplified conceptual diagram. The values of the actual circuit elements are proprietary.

    If it helps, the differential input impedance (between VIN+ and VIN-) is very close to 20Ohms in series with 7pF, in track mode, which is the state of the input right up to the sampling instant.

    What sample rate are you using?

    Can you share your schematic?

    Thank you.


  • Hi Dougl,

    Thank you for your help.

    We are using your evaluation board EVAL-AD9656 with the sample frequency set at 125MHz (pdf joined).

    We have already implement the track and hold part with the 20 ohms in series with 7pF model in our LTSpice simulation.

    During one half period (4ns) the ADC is in tracking mode (Csample is loaded at the voltage value set in the input) and during the second half period (4ns) the ADC is in holding mode (Csample is read by the ADC part system).

    But, we don't have any information in the datasheet concerning the status of Csample during holding mode (discharge complete, partial etc.)

    What is the value of Csample when the ADC switch from holding mode to tracking mode?

    We suspect that these capacitors are not completely charged at the input voltage set when the ADC goes in holding mode.

    Best regards,

  • 0
    •  Analog Employees 
    on Nov 12, 2019 11:46 PM over 1 year ago in reply to D@niel

    Thanks D@niel.

    Please note that at the ADC inputs you might observe a lot of "glitches" due to activity in the switched capacitor input circuit. This is expected and does not cause a problem.

    Thank you.


  • Hi Dougl,

    We have resolved our problem with the AD9656 AD Evaluation Board. In fact, we have changed the AD9656 of the board because the internal reference voltage was damaged because the serigraphy of board contained an error.

    Now, we don't understand why we don't have a good dynamic result with our board.
    Below the step description :

    1. We have validate our FPGA and embedded code with the evaluation board AD9656.
    Gene Keysight 81150A sinus @10MHz/bin 4,688Vpp  + elliptic filter 6 order (6dB att @10MHz/bin)

    Result with our app software (4096 points captured @Fs=125MSPS)
    Fund : -11,11 dB
    H2 : -99,16 dB  --> -88,05 dBc
    H3 : -98,77 dB --> -87,66 dBc

    These results are still far from what you get (probably due to the setup) but are acceptable for us.

    2. However, we don't obtain good result with our front-end.

    Same as before

    Result with our app software (4096 points captured @Fs=125MSPS)

    ChA (with ADA4930-1)
    Fund : -10,7 dB
    H2 : -72,55 dB  --> -61,85 dBc
    H3 : -84,28 dB --> -73,58 dBc

    ChB (with AD8138)
    Fund : -10,57 dB
    H2 : -87,95 dB  --> -77,38 dBc
    H3 : -90,01 dB --> -79,44 dBc

    Very far from expected value of AD8138 and ADA4930-1 datasheet.

    Very far from expected value of ADA4930-1 datasheet.

    Questions :

    - Do you have an idea to retrieve good performance as the datasheet?

    - Although the ADA4930-1 datasheet seems better compared to AD8138 we don't observe that. Why ?

    Thank you in advance for your reply.


  • 0
    •  Analog Employees 
    on Jun 16, 2020 2:40 AM 10 months ago in reply to D@niel

    Hi D@niel,

    The ADC input common mode is being applied through 390Ohm resistors. Are you able to measure the input common mode voltage at the ADC inputs? Could you try reducing these VCM resistors to about 100 Ohms to see if that makes any difference?

    Your signal generator for both setups is "Keysight 81150A sinus @10MHz/bin 4,688Vpp  + elliptic filter 6 order (6dB att @10MHz/bin)".

    • Does 10MHz/bin mean that your signal frequency is 10MHz?
    • Is the elliptic filter's pass band centered at 10MHz?
    • It looks like your amplifiers are configured for a gain of 1. I see that the fundamental amplitude is about -11dB. How are you attenuating your signal to be within the full-scale range of the AD9656?

    Thank you.


  • Hi Doug,

    Thank your for your reply.

    In fact, we have checked all polarization voltage at different points of the input structure.
    The measure result of the input common mode voltage at the ADC inputs is 0,878V with internal ADC Vref equal to 1,392V.

    We have already reduce the resistive load in our old design but the dynamic range is lower.
    Result with 100R and AD8138
    Fund : -10,67 dB
    H2 : -83,58 dB --> -72,91 dBc
    H3 : -86,43 dB --> -75,76 dBc
    As you can see the result is lower than before with 390R.
    We have chosen this value of load (780 R) in order to obtain good performance in term of distorsion. In the datasheet of AD8138 best result with 800R load.

    Concerning the other points :

    - Fin = Bin x int (Fin_required / Bin) with Bin = Fs/N
    Fs is the sample frequency 125MSPS, N is the number of point 4096 and Fin_required is 10MHz.
    So, 10MHz/bin mean Fin = 9,979248046875‬ MHz.

    - Ellipic filter is used to concerve only the fundamental signal at Fin and suppress H2 and H3.

    - You right. We have not yet calibrate the app and we make only an FFT. For the moment, we want to obtain a good dynamic (close as possible of the datasheet).

  • 0
    •  Analog Employees 
    on Jun 17, 2020 11:18 PM 9 months ago in reply to D@niel

    Hi D@niel,

    I'll ask the amplifier guys if they have any thoughts on your circuit.


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