AD9656 dynamic level

Hi,

We are using AD9656 evaluation board and we carry out the following test.

We configure the ADC register correctly with 2,8Vpp input span, quick configuration : One ADC per lane etc.

We put a sinus signal of 1MHz on the input A and check the digital value for different voltage Vpp values.

When we increase the voltage between 100mVpp and 2,5Vpp, from a certain value, we note that the digitalized result is lower than the expected result.
We see a compression of data at the end of the curve of data point instead of linear curve.

This is due to the track and hold part of ADC, because we have check the analog front-end and it's work well.

Can we have more information of track and hold structure?
What is the value of CPAR and CSAMPLE?
We want to make a simulation of this part with LTSpice, but we don't have information of how the ADC take the value of CSAMPLE (discharge of CSAMPLE complete, partial etc.).
Where the outputs of the ADC input structure is connected?

Thank you in advance for your answers.

Best regards,

Parents
  • 0
    •  Analog Employees 
    on Nov 11, 2019 5:23 PM over 1 year ago

    Hi Daniel,

    Thank you for using the AD9656.

    Figure 46 is a very simplified conceptual diagram. The values of the actual circuit elements are proprietary.

    If it helps, the differential input impedance (between VIN+ and VIN-) is very close to 20Ohms in series with 7pF, in track mode, which is the state of the input right up to the sampling instant.

    What sample rate are you using?

    Can you share your schematic?

    Thank you.

    Doug

Reply
  • 0
    •  Analog Employees 
    on Nov 11, 2019 5:23 PM over 1 year ago

    Hi Daniel,

    Thank you for using the AD9656.

    Figure 46 is a very simplified conceptual diagram. The values of the actual circuit elements are proprietary.

    If it helps, the differential input impedance (between VIN+ and VIN-) is very close to 20Ohms in series with 7pF, in track mode, which is the state of the input right up to the sampling instant.

    What sample rate are you using?

    Can you share your schematic?

    Thank you.

    Doug

Children
  • Hi Dougl,

    Thank you for your help.

    We are using your evaluation board EVAL-AD9656 with the sample frequency set at 125MHz (pdf joined).

    We have already implement the track and hold part with the 20 ohms in series with 7pF model in our LTSpice simulation.

    During one half period (4ns) the ADC is in tracking mode (Csample is loaded at the voltage value set in the input) and during the second half period (4ns) the ADC is in holding mode (Csample is read by the ADC part system).

    But, we don't have any information in the datasheet concerning the status of Csample during holding mode (discharge complete, partial etc.)

    What is the value of Csample when the ADC switch from holding mode to tracking mode?

    We suspect that these capacitors are not completely charged at the input voltage set when the ADC goes in holding mode.

    Best regards,

    PDF
  • 0
    •  Analog Employees 
    on Nov 12, 2019 2:48 AM over 1 year ago in reply to D@niel

    Hi D@niel,

    I believe the sampling capacitor gets reset to have both sides at AVDD/2, so that means no voltage across the capacitor, before entering track mode. I'll double check that with one of the designers.

    The board you are using is the same board design that we used to take datasheet measurements with. Any non-settling of the analog inputs before sampling are already accounted for in the datasheet specifications.

    How much "compression" are you seeing?

    Thank you.

    Doug

  • Hi Dougl,

    We must perform the test again but we had noted a compression of approximately 0,3 dB.

    We will redo measurements for different voltage between 0 to 2,8Vpp (span configured accordingly) at 1MHz for different points.

    First measure in the SMA connector input, second in the differential ADC input : with spectrum analyzer and differential probe.
    And also see the raw result of conversion in 2 complement mode.

    I will put the results in excel sheet, trace the curve and i will transmit to you.

    Best regards.

  • 0
    •  Analog Employees 
    on Nov 12, 2019 11:46 PM over 1 year ago in reply to D@niel

    Thanks D@niel.

    Please note that at the ADC inputs you might observe a lot of "glitches" due to activity in the switched capacitor input circuit. This is expected and does not cause a problem.

    Thank you.

    Dou8g

  • Hi Dougl,

    We have resolved our problem with the AD9656 AD Evaluation Board. In fact, we have changed the AD9656 of the board because the internal reference voltage was damaged because the serigraphy of board contained an error.

    Now, we don't understand why we don't have a good dynamic result with our board.
    Below the step description :

    1. We have validate our FPGA and embedded code with the evaluation board AD9656.
    Setup
    Gene Keysight 81150A sinus @10MHz/bin 4,688Vpp  + elliptic filter 6 order (6dB att @10MHz/bin)

    Result with our app software (4096 points captured @Fs=125MSPS)
    Fund : -11,11 dB
    H2 : -99,16 dB  --> -88,05 dBc
    H3 : -98,77 dB --> -87,66 dBc

    These results are still far from what you get (probably due to the setup) but are acceptable for us.

    2. However, we don't obtain good result with our front-end.

    Setup
    Same as before

    Result with our app software (4096 points captured @Fs=125MSPS)

    ChA (with ADA4930-1)
    Fund : -10,7 dB
    H2 : -72,55 dB  --> -61,85 dBc
    H3 : -84,28 dB --> -73,58 dBc

    ChB (with AD8138)
    Fund : -10,57 dB
    H2 : -87,95 dB  --> -77,38 dBc
    H3 : -90,01 dB --> -79,44 dBc

    Very far from expected value of AD8138 and ADA4930-1 datasheet.

    Very far from expected value of ADA4930-1 datasheet.

    Questions :

    - Do you have an idea to retrieve good performance as the datasheet?

    - Although the ADA4930-1 datasheet seems better compared to AD8138 we don't observe that. Why ?

    Thank you in advance for your reply.

    Best,