AD9656 front end for narrow-band

Hi Daniel,

I have not worked much with the narrow band configurations, but I have kept the inductor right next to the shunt capacitor.

I'm not an expert but the way I'm thinking about this is that the inductor will resonate with the equivalent input capacitance (on board + ADC input) at your desired frequency. Having the 33 Ohms between the inductor and  equivalent capacitance will de-Q the resonant circuit and seemingly diminish the effect you are trying to achieve.

Fortunately, it looks like you can experiment with it both ways, with the AD9656 evaluation board.

Please let us know how it goes.

Thanks,

Doug

Hi Doug,

I have some news and questions.

Mentioned circuit with impedance transformation works fine. There is no degradation in achieved parameters.

We have two eval boards with AD9656. The first one has modified inputs with transformators. We observe same DC offset for both boards with signal on output and without a signal. The fund DC power is circa -36 to -42 dBFS. I have tried compensate it with register 0x10 (offset adjust). Sadly it's limited value (+127 to -128) when we need greater value (300 to 400) so it seems it will have to be fixed in FPGA.

We have finished test platform with ultra low noise clock and signal source so I tried to find out the limits of AD9656. Both sources are 10dBm sinus with phase noise circa 10Hz@-100dBc/Hz, 100Hz@-135dBc/Hz, 1kHz@-157dBc/Hz, noise floor -174dBc/Hz. The actual clock source with HMC7044 (CVHD-950 VCXO) has been replaced by this clock source with ultra low phase noise.

Achieved broadband SNR/NSD is slightly better by 2 to 3 dB, but we are interested in close in noise around carrier signal when its power is close to fullscale.

Attached picture is spectrum of "close in"

As you can see...the observed increased close in noise by 20dB is not caused by phase noise of clock source or test signal but maybe it is caused by internal flicker noise of ADc or some unknow source (power supply of ADc?). We would like to have this close in noise as low as possible atleast for 1kHz offset.

Do you think we have achieved the limit of AD9656 (flicker noise caused by implementation of clock sampler)? I will try translate clock sinus to higher SR with LTC6957 to see if it has an impact.

Thanks,

Daniel

Hi Daniel,

I can try to setup AD9656 on my bench at your test frequencies, using the same type of lab equipment that was used to take datasheet measurements, to see how my close-in FFT looks compared to yours.

From the VisualAnalog information on the left of your picture, it looks like you have:
122.76Msps sample rate
22.76MHz input frequency (or is this aliasing/folding back to 22.76MHz?)

Is this correct?

Thanks,

Doug

Hi Doug,

that would be great!

I confirm the value of sample rate.

Input frequency is 100MHz so it is alias.

Best regards,

Daniel

Hi Daniel,

I think my FFT looks quite similar to yours. Your signal sources must be about the same quality as mine.

AD9656_122p76Msps_100MHz_N1p97dBFS_ZoomIn.tif

I don't know that you'll be able to easily improve much beyond this.

Thanks,

Doug

Hello Doug,

Thank you for measurement!

So mother nature isn't beaten and flicker noise rules...it seems there is not so much we can do about it with AD9656. 

Is possible with another ADI ADc (pipeline with at least 125MSPS, JESD204(B) interface) we can achieve better close-in FFT performance?

This feature is not easily obtained from datasheet.

Thanks,

Daniel

Hi Daniel,

Yes, mother nature is hard to defeat!

The ADI application engineers each support a subset of the high speed ADC portfolio. AD9656 is the only 125Msps JESD204B ADC that I support. There are other JESD204B ADCs that have a higher maximum sample rate but will work at 125Msps, but I do not have the boards for those to try.

One thought is that, if the skirt around the fundamental is clock phase noise related, then there are a couple of things we could try.

1. filter the clock
2. apply a higher frequency clock and use the AD9656 clock frequency divider to divide down to 122.76MHz. The higher edge rates of the higher frequency typically result in reduced jitter.

These are admittedly a long-shot, but I'll try to check this and report back to you. It might not be until next week before I can get to this.

I hope you have a nice weekend.

Doug

Hello Doug,

I tried your suggesiton with clock divider usage. I have set up the our HMC7044 to generate 1Ghz and AD9656 internal divider to 8. AD9656 reports internal JESD PLL lock but onboard multiplier AD9553 is not locked (green led doesn't light up). The problem is that I don't know how to access onboard multiplier and divider from your provided software. According to wiki page and forum threads the access is made from VisualAnalog somehow.

Regarding the point about filtering the clock - I'm not sure what you mean.

By the way...Is possible consult some our proprietary stuff (concerning AD9656) with you by e-mail?

I hope you had a nice weekend.

Thanks and regards,

Daniel

Hi Daniel,

Thanks for trying the clock divider. On the ADI board VisualAnalog is supposed to read the AD9656 clock divider value and apply the same divide value to the on-board AD9508. The AD9508 provides the divided clock to the AD9553, so the AD9553 will still see the 125MHz clock. There is a reset button for AD9553 on the AD9656 evaluation board. Have you tried this?

Filtering the clock is just adding a series band pass filter (BPF) to the clock. For a 122.76MHz clock, you would use a BPF with a center frequency of about 122.76MHz (probably 120MHz or 125MHz would work fine).

I'll send you an email soon.

Thank you.

Doug

Hello Doug,

I tried what you advised but without a luck.

On EVALEZ board I see only LED 2 D802 is light up and LED 1 D801 blinking weakly. When I switch from 1GHz to 125MHz and set divider to 1, refresh app, the all LEDs light up and app starts to work.

Here is our config when we are trying 1GHz.

Regarding our close-in performace problem.

Colleaque advised to look at reference of the AD9656. Do you think it can have an impact? I don't have any source of low-noise reference for external vref at the moment. The on-board external vref with AD822 doesn't seem suitable with its noise. Maybe we could try indirectly affect the noise of Vref with increasing the capacity value of C406x (Vcm). What do you think?

Tommorow I will have ready our kit with LTC6957 so we will see if it have an impact.

Thanks and regards,

Daniel