We would like to use AD9656 for narrow-band application (circa 90MHz - 110MHz). Problem is that AD9656 has high fullscale for our application.
We have good experience with interfacing ADc with buffered inputs where transformers with 1:4 impedance ratio are used to achieve lower fullscale (see MT-006, MT-228 and AN-935).
The AD9656 has switched-capacitor input so this solution is more challenging. Do you think it is solvable? If so can you please provide input impedance parameter for band of interest?
Thanks and regards
Do you think that "0th LSB" replaced with overrange flag will affect SNR of the 16-bit AD9656?
I could use it for some calibration mode or AGC - just check that there is no need to atenuate the input signal and then re-initialize ADC and JESD to full 16 bit mode for example. My application will feed this ADc close to -1dBFS with high probability of overriding the input. So some kind of detection of -1dBFS or above 0dBFS could be very handy.
I was hoping that the AD9656 has some undocumented registers for this task (like threshold for overrange flag etc).
Regards and thanks,
SNR will be affected by removing the LSB but not by much. I believe the noise is dominated by thermal noise rather than quantization noise, but still there would be a small effect. How much can you tolerate?
I'm sorry but I am not aware of any undocumented registers to help with overrange.
Thank your for answers.
We have achieved sufficient SNR performance with AD9656 in our application. Few losses in dB in SNR because of removing LSB should be fine but first I have to evaluate.
First we have to decrease fullscale of AD9656 with impedance transformation mentioned above. It will take a time.
Regarding your 1:4 transformer, though the transformer will not add noise, it will "step-up" noise as well as the intended signal so I don't see how you can get an SNR benefit by going through a transformer.
I know we already discussed Register 0x18 to decrease the full scale of the AD9656. This might be a quicker solution.
Of course, you know best for your application.
I'm sorry for bad interpretation. You are right - the SNR performance should be same but with lower fullscale we achieve better noise figure (SNR value remains same ideally).
I would like to ask you for taking a look at designed schematics. I will test it on modified evaluation board AD9656EVM.
I'm not sure about 33ohm resistors placement. Is it better place them between inductor and 5p capacitor to reduce kickback from ADC input?