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# AD9656 front end for narrow-band

Hello

We would like to use AD9656 for narrow-band application (circa 90MHz - 110MHz). Problem is that AD9656 has high fullscale for our application.

We have good experience with interfacing ADc with buffered inputs where transformers with 1:4 impedance ratio are used to achieve lower fullscale (see MT-006, MT-228 and AN-935).

The AD9656 has switched-capacitor input so this solution is more challenging. Do you think it is solvable? If so can you please provide input impedance parameter for band of interest?

Thanks and regards

Daniel

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• Hi Daniel,

Thank you for considering the AD9656.

The input impedance information is on the AD9656 product page, in the Tools & Simulations section https://www.analog.com/en/products/ad9656.html#product-tools . This shows the impedance in the "track" phase" of the switched cap input, which is the phase of interest because it is the mode that leads up to the sampling instant. The file shows two equivalent simplified representations of the input impedance. The series RL representation is 20Ohms in series with 7pF. This is a good representation across a wide frequency range. For narrow band applications some users find it helpful to use the parallel equivalent representation. You choose your frequency of interest in the AD9656_AINDIFFZ tab of the impedance Excel file, and find the equivalent R and C at your frequency of interest. For example 100MHz corresponds to 2.6kOhms in parallel with 6.95pF. Then it is easier as a first pass to calculate a parallel inductance at the input, that counters the equivalent parallel capacitance.

If the input full-scale is too high for your application, you can use Register 0x18 Bits[2:0] to adjust the full scale range downward. This (Bits[2:0]) is a back end digital adjustment and does not affect the analog portion. For example, writing Register 0x18 = 0x00 results in an input full scale voltage of 1Vpp_differential. Please see Table 19 in the AD9656 datasheet for more information.

Thank you.

Doug

• Hello Doug

Thank you for provided information.

We need to preserve SNR performance of AD9656. I admit I didn't understant bits 2:0 in register 0x18. I believed that could affect NSD/NF performance somehow so I let it be on 100%. That's why we would like to go with impedance transformation solution because it is "noise free".

Anyway we have got AD9656 eval kit so I will give it try.

Dan

• Hi Daniel,

I can try to setup AD9656 on my bench at your test frequencies, using the same type of lab equipment that was used to take datasheet measurements, to see how my close-in FFT looks compared to yours.

122.76Msps sample rate
22.76MHz input frequency (or is this aliasing/folding back to 22.76MHz?)

Is this correct?

Thanks,

Doug

• Hi Doug,

that would be great!

I confirm the value of sample rate.

Input frequency is 100MHz so it is alias.

Best regards,

Daniel

• Hi Daniel,

I think my FFT looks quite similar to yours. Your signal sources must be about the same quality as mine.

I don't know that you'll be able to easily improve much beyond this.

Thanks,

Doug

• Hello Doug,

Thank you for measurement!

So mother nature isn't beaten and flicker noise rules...it seems there is not so much we can do about it with AD9656.

Is possible with another ADI ADc (pipeline with at least 125MSPS, JESD204(B) interface) we can achieve better close-in FFT performance?

This feature is not easily obtained from datasheet.

Thanks,

Daniel

• Hi Daniel,

Yes, mother nature is hard to defeat!

The ADI application engineers each support a subset of the high speed ADC portfolio. AD9656 is the only 125Msps JESD204B ADC that I support. There are other JESD204B ADCs that have a higher maximum sample rate but will work at 125Msps, but I do not have the boards for those to try.

One thought is that, if the skirt around the fundamental is clock phase noise related, then there are a couple of things we could try.

1. filter the clock
2. apply a higher frequency clock and use the AD9656 clock frequency divider to divide down to 122.76MHz. The higher edge rates of the higher frequency typically result in reduced jitter.

These are admittedly a long-shot, but I'll try to check this and report back to you. It might not be until next week before I can get to this.

I hope you have a nice weekend.

Doug

• Hello Doug,

I tried your suggesiton with clock divider usage. I have set up the our HMC7044 to generate 1Ghz and AD9656 internal divider to 8. AD9656 reports internal JESD PLL lock but onboard multiplier AD9553 is not locked (green led doesn't light up). The problem is that I don't know how to access onboard multiplier and divider from your provided software. According to wiki page and forum threads the access is made from VisualAnalog somehow.

Regarding the point about filtering the clock - I'm not sure what you mean.

By the way...Is possible consult some our proprietary stuff (concerning AD9656) with you by e-mail?

I hope you had a nice weekend.

Thanks and regards,

Daniel

• Hi Daniel,

Thanks for trying the clock divider. On the ADI board VisualAnalog is supposed to read the AD9656 clock divider value and apply the same divide value to the on-board AD9508. The AD9508 provides the divided clock to the AD9553, so the AD9553 will still see the 125MHz clock. There is a reset button for AD9553 on the AD9656 evaluation board. Have you tried this?

Filtering the clock is just adding a series band pass filter (BPF) to the clock. For a 122.76MHz clock, you would use a BPF with a center frequency of about 122.76MHz (probably 120MHz or 125MHz would work fine).

I'll send you an email soon.

Thank you.

Doug

• Hello Doug,

I tried what you advised but without a luck.

On EVALEZ board I see only LED 2 D802 is light up and LED 1 D801 blinking weakly. When I switch from 1GHz to 125MHz and set divider to 1, refresh app, the all LEDs light up and app starts to work.

Here is our config when we are trying 1GHz.

Regarding our close-in performace problem.

Colleaque advised to look at reference of the AD9656. Do you think it can have an impact? I don't have any source of low-noise reference for external vref at the moment. The on-board external vref with AD822 doesn't seem suitable with its noise. Maybe we could try indirectly affect the noise of Vref with increasing the capacity value of C406x (Vcm). What do you think?

Tommorow I will have ready our kit with LTC6957 so we will see if it have an impact.

Thanks and regards,

Daniel

• Hi Daniel,

Certainly lower noise on VREF will help, but it seems to me that this will reduce broadband noise and not necessarily the close in 1/f and phase-noise.

I'll try to setup my bench and give the clock divider a try, but I won't be able to get to this for a few days.

Thanks.

Doug

• Hi Doug,

We have tried filter Vref and Vcm. It has zero impact.

Finally we have used LTC6957 to increase slew rate of our sinus clock source. We believe it has same effect as usage divided 1GHz clock. Unfortunately it had no effect on our close-in SNR problem. So I think it is not neccessary to try experiment with clock divider from your side.

Thanks and regards,

Daniel

• Hi Doug,

We have tried filter Vref and Vcm. It has zero impact.

Finally we have used LTC6957 to increase slew rate of our sinus clock source. We believe it has same effect as usage divided 1GHz clock. Unfortunately it had no effect on our close-in SNR problem. So I think it is not neccessary to try experiment with clock divider from your side.

Thanks and regards,

Daniel

Children
• Hi Daniel,

Thank you for the information, and for your thorough efforts. Thanks again for considering the AD9656.