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# AD9656 front end for narrow-band

Hello

We would like to use AD9656 for narrow-band application (circa 90MHz - 110MHz). Problem is that AD9656 has high fullscale for our application.

We have good experience with interfacing ADc with buffered inputs where transformers with 1:4 impedance ratio are used to achieve lower fullscale (see MT-006, MT-228 and AN-935).

The AD9656 has switched-capacitor input so this solution is more challenging. Do you think it is solvable? If so can you please provide input impedance parameter for band of interest?

Thanks and regards

Daniel

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• Hi Daniel,

Thank you for considering the AD9656.

The input impedance information is on the AD9656 product page, in the Tools & Simulations section https://www.analog.com/en/products/ad9656.html#product-tools . This shows the impedance in the "track" phase" of the switched cap input, which is the phase of interest because it is the mode that leads up to the sampling instant. The file shows two equivalent simplified representations of the input impedance. The series RL representation is 20Ohms in series with 7pF. This is a good representation across a wide frequency range. For narrow band applications some users find it helpful to use the parallel equivalent representation. You choose your frequency of interest in the AD9656_AINDIFFZ tab of the impedance Excel file, and find the equivalent R and C at your frequency of interest. For example 100MHz corresponds to 2.6kOhms in parallel with 6.95pF. Then it is easier as a first pass to calculate a parallel inductance at the input, that counters the equivalent parallel capacitance.

If the input full-scale is too high for your application, you can use Register 0x18 Bits[2:0] to adjust the full scale range downward. This (Bits[2:0]) is a back end digital adjustment and does not affect the analog portion. For example, writing Register 0x18 = 0x00 results in an input full scale voltage of 1Vpp_differential. Please see Table 19 in the AD9656 datasheet for more information.

Thank you.

Doug

• Hello Doug

Thank you for provided information.

We need to preserve SNR performance of AD9656. I admit I didn't understant bits 2:0 in register 0x18. I believed that could affect NSD/NF performance somehow so I let it be on 100%. That's why we would like to go with impedance transformation solution because it is "noise free".

Anyway we have got AD9656 eval kit so I will give it try.

Dan

• Hi Dan,

I hope your evaluation goes well. Please let us know if you have any questions.

Thanks,

Doug

• Hi Doug,

I have tried span adjustment to 50% and fed the ADc with -1dBFS (FS = 4dBm, Vref 1V). Compared to 10dBm fullscale (span 100%) I observe some degradation in SNR but it is still usable for our application.

I have question about override/overrange detection funcionality of the AD9656. According to datasheet the [15:14] bits from JESD data output can be used for overrange and underrange flags. How does overrange indicator work? How can I set the thresholds? I lack more information in document about this.

Thanks and regards,

Dan

• Hi Dan,

The AD9656 is a 16 bit ADC. As such the JESD204B parameter N (resolution) must be 16 for full performance. The JESD204B parameter N' (number of bits per sample) is also 16.

This equation must be satisfied: N' = N + CS + T
N' = number of bits per sample (16 for AD9656)
N = converter resolution (default is 16 for AD9656)
CS = number of control bits (can contain overrange information)
T = number of tail bits, which are bits to fill incomplete nibbles

As you can see, in AD9656's default configuration as a 16 bit ADC (N' = N = 16), there is no room for control bits that could contain overrange information. The AD9656 RevA datasheet states this on page 26: "C = control bit (overrange, overflow, underflow; unavailable in the AD9656 default mode)".

Can you tolerate lower SNR to make room for control bits?

Thank you.

Doug

• Hi Doug,

Do you think that "0th LSB" replaced with overrange flag will affect SNR of the 16-bit AD9656?

I could use it for some calibration mode or AGC - just check that there is no need to atenuate the input signal and then re-initialize ADC and JESD to full 16 bit mode for example. My application will feed this ADc close to -1dBFS with high probability of overriding the input. So some kind of detection of -1dBFS or above 0dBFS could be very handy.

I was hoping that the AD9656 has some undocumented registers for this task (like threshold for overrange flag etc).

Regards and thanks,

Dan

• Hi Dan,

SNR will be affected by removing the LSB but not by much. I believe the noise is dominated by thermal noise rather than quantization noise, but still there would be a small effect. How much can you tolerate?

I'm sorry but I am not aware of any undocumented registers to help with overrange.

Doug

• Hello Doug,

We have achieved sufficient SNR performance with AD9656 in our application. Few losses in dB in SNR because of removing LSB should be fine but first I have to evaluate.

First we have to decrease fullscale of AD9656 with impedance transformation mentioned above. It will take a time.

Dan

• Hi Dan,

Regarding your 1:4 transformer, though the transformer will not add noise, it will "step-up" noise as well as the intended signal so I don't see how you can get an SNR benefit by going through a transformer.

I know we already discussed Register 0x18 to decrease the full scale of the AD9656. This might be a quicker solution.

Of course, you know best for your application.

Doug

• Hi Dan,

Regarding your 1:4 transformer, though the transformer will not add noise, it will "step-up" noise as well as the intended signal so I don't see how you can get an SNR benefit by going through a transformer.

I know we already discussed Register 0x18 to decrease the full scale of the AD9656. This might be a quicker solution.

Of course, you know best for your application.

Doug

Children
• Hi Doug,

I'm sorry for bad interpretation. You are right - the SNR performance should be same but with lower fullscale we achieve better noise figure (SNR value remains same ideally).

I would like to ask you for taking a look at designed schematics. I will test it on modified evaluation board AD9656EVM.

I'm not sure about 33ohm resistors placement. Is it better place them between inductor and 5p capacitor to reduce kickback from ADC input?

Thanks and regards

Daniel

• Hi Daniel,

I have not worked much with the narrow band configurations, but I have kept the inductor right next to the shunt capacitor.

I'm not an expert but the way I'm thinking about this is that the inductor will resonate with the equivalent input capacitance (on board + ADC input) at your desired frequency. Having the 33 Ohms between the inductor and  equivalent capacitance will de-Q the resonant circuit and seemingly diminish the effect you are trying to achieve.

Fortunately, it looks like you can experiment with it both ways, with the AD9656 evaluation board.

Please let us know how it goes.

Thanks,

Doug

• Hi Doug,

I have some news and questions.

Mentioned circuit with impedance transformation works fine. There is no degradation in achieved parameters.

We have two eval boards with AD9656. The first one has modified inputs with transformators. We observe same DC offset for both boards with signal on output and without a signal. The fund DC power is circa -36 to -42 dBFS. I have tried compensate it with register 0x10 (offset adjust). Sadly it's limited value (+127 to -128) when we need greater value (300 to 400) so it seems it will have to be fixed in FPGA.

We have finished test platform with ultra low noise clock and signal source so I tried to find out the limits of AD9656. Both sources are 10dBm sinus with phase noise circa 10Hz@-100dBc/Hz, 100Hz@-135dBc/Hz, 1kHz@-157dBc/Hz, noise floor -174dBc/Hz. The actual clock source with HMC7044 (CVHD-950 VCXO) has been replaced by this clock source with ultra low phase noise.

Achieved broadband SNR/NSD is slightly better by 2 to 3 dB, but we are interested in close in noise around carrier signal when its power is close to fullscale.

Attached picture is spectrum of "close in"

As you can see...the observed increased close in noise by 20dB is not caused by phase noise of clock source or test signal but maybe it is caused by internal flicker noise of ADc or some unknow source (power supply of ADc?). We would like to have this close in noise as low as possible atleast for 1kHz offset.

Do you think we have achieved the limit of AD9656 (flicker noise caused by implementation of clock sampler)? I will try translate clock sinus to higher SR with LTC6957 to see if it has an impact.

Thanks,

Daniel

• Hi Daniel,

I can try to setup AD9656 on my bench at your test frequencies, using the same type of lab equipment that was used to take datasheet measurements, to see how my close-in FFT looks compared to yours.

122.76Msps sample rate
22.76MHz input frequency (or is this aliasing/folding back to 22.76MHz?)

Is this correct?

Thanks,

Doug

• Hi Doug,

that would be great!

I confirm the value of sample rate.

Input frequency is 100MHz so it is alias.

Best regards,

Daniel

• Hi Daniel,

I think my FFT looks quite similar to yours. Your signal sources must be about the same quality as mine.

I don't know that you'll be able to easily improve much beyond this.

Thanks,

Doug

• Hello Doug,

Thank you for measurement!

So mother nature isn't beaten and flicker noise rules...it seems there is not so much we can do about it with AD9656.

Is possible with another ADI ADc (pipeline with at least 125MSPS, JESD204(B) interface) we can achieve better close-in FFT performance?

This feature is not easily obtained from datasheet.

Thanks,

Daniel

• Hi Daniel,

Yes, mother nature is hard to defeat!

The ADI application engineers each support a subset of the high speed ADC portfolio. AD9656 is the only 125Msps JESD204B ADC that I support. There are other JESD204B ADCs that have a higher maximum sample rate but will work at 125Msps, but I do not have the boards for those to try.

One thought is that, if the skirt around the fundamental is clock phase noise related, then there are a couple of things we could try.

1. filter the clock
2. apply a higher frequency clock and use the AD9656 clock frequency divider to divide down to 122.76MHz. The higher edge rates of the higher frequency typically result in reduced jitter.

These are admittedly a long-shot, but I'll try to check this and report back to you. It might not be until next week before I can get to this.

I hope you have a nice weekend.

Doug

• Hello Doug,

I tried your suggesiton with clock divider usage. I have set up the our HMC7044 to generate 1Ghz and AD9656 internal divider to 8. AD9656 reports internal JESD PLL lock but onboard multiplier AD9553 is not locked (green led doesn't light up). The problem is that I don't know how to access onboard multiplier and divider from your provided software. According to wiki page and forum threads the access is made from VisualAnalog somehow.

Regarding the point about filtering the clock - I'm not sure what you mean.

By the way...Is possible consult some our proprietary stuff (concerning AD9656) with you by e-mail?

I hope you had a nice weekend.

Thanks and regards,

Daniel

• Hi Daniel,

Thanks for trying the clock divider. On the ADI board VisualAnalog is supposed to read the AD9656 clock divider value and apply the same divide value to the on-board AD9508. The AD9508 provides the divided clock to the AD9553, so the AD9553 will still see the 125MHz clock. There is a reset button for AD9553 on the AD9656 evaluation board. Have you tried this?

Filtering the clock is just adding a series band pass filter (BPF) to the clock. For a 122.76MHz clock, you would use a BPF with a center frequency of about 122.76MHz (probably 120MHz or 125MHz would work fine).

I'll send you an email soon.

Thank you.

Doug