We would like to use AD9656 for narrow-band application (circa 90MHz - 110MHz). Problem is that AD9656 has high fullscale for our application.
We have good experience with interfacing ADc with buffered inputs where transformers with 1:4 impedance ratio are used to achieve lower fullscale (see MT-006, MT-228 and AN-935).
The AD9656 has switched-capacitor input so this solution is more challenging. Do you think it is solvable? If so can you please provide input impedance parameter for band of interest?
Thanks and regards
Thank you for considering the AD9656.
The input impedance information is on the AD9656 product page, in the Tools & Simulations section https://www.analog.com/en/products/ad9656.html#product-tools . This shows the impedance in the "track" phase" of the switched cap input, which is the phase of interest because it is the mode that leads up to the sampling instant. The file shows two equivalent simplified representations of the input impedance. The series RL representation is 20Ohms in series with 7pF. This is a good representation across a wide frequency range. For narrow band applications some users find it helpful to use the parallel equivalent representation. You choose your frequency of interest in the AD9656_AINDIFFZ tab of the impedance Excel file, and find the equivalent R and C at your frequency of interest. For example 100MHz corresponds to 2.6kOhms in parallel with 6.95pF. Then it is easier as a first pass to calculate a parallel inductance at the input, that counters the equivalent parallel capacitance.
If the input full-scale is too high for your application, you can use Register 0x18 Bits[2:0] to adjust the full scale range downward. This (Bits[2:0]) is a back end digital adjustment and does not affect the analog portion. For example, writing Register 0x18 = 0x00 results in an input full scale voltage of 1Vpp_differential. Please see Table 19 in the AD9656 datasheet for more information.
Thank you for provided information.
Add to full-scale...
We need to preserve SNR performance of AD9656. I admit I didn't understant bits 2:0 in register 0x18. I believed that could affect NSD/NF performance somehow so I let it be on 100%. That's why we would like to go with impedance transformation solution because it is "noise free".
Anyway we have got AD9656 eval kit so I will give it try.
I hope your evaluation goes well. Please let us know if you have any questions.
I have tried span adjustment to 50% and fed the ADc with -1dBFS (FS = 4dBm, Vref 1V). Compared to 10dBm fullscale (span 100%) I observe some degradation in SNR but it is still usable for our application.
I have question about override/overrange detection funcionality of the AD9656. According to datasheet the [15:14] bits from JESD data output can be used for overrange and underrange flags. How does overrange indicator work? How can I set the thresholds? I lack more information in document about this.
Thanks and regards,
The AD9656 is a 16 bit ADC. As such the JESD204B parameter N (resolution) must be 16 for full performance. The JESD204B parameter N' (number of bits per sample) is also 16.
This equation must be satisfied: N' = N + CS + TN' = number of bits per sample (16 for AD9656)N = converter resolution (default is 16 for AD9656)CS = number of control bits (can contain overrange information)T = number of tail bits, which are bits to fill incomplete nibbles
As you can see, in AD9656's default configuration as a 16 bit ADC (N' = N = 16), there is no room for control bits that could contain overrange information. The AD9656 RevA datasheet states this on page 26: "C = control bit (overrange, overflow, underflow; unavailable in the AD9656 default mode)".
Can you tolerate lower SNR to make room for control bits?