I have a question about the DC1945A Evaluationboard. I use the DC1945A: LTC2185 and LTC6409 COMBO BOARD to interface it with my zynq7000 FPGA. I read the Datasheets about the components in detail but there is an issue, which i can't understand so far. The output of the LVDS drivers should have an maximum output swing of 400mV. I measured it with an 100Mhz, 200MSA/s oscilloscope and I saw the signal wave going from 0V to 3,3V. The drivers of my FPGA support LVDS_25 and TMDS standard but i thought the LVDS would have +-400mV with an offset voltage around 1,2V like the datasheets say. I wonder if there is an issue with the electronic.
My configurations are:
Program Mode: PAR (JP1)Duty cycle stab.: EN (JP2)SHDN: DIS (JP3)NAP: EN (JP4)
My Clock is a 10 Mhz 3.3V oscillator used in single ended mode.The I and Q Inputs are not connected.
AMP VCC is powered with 3,3VDigital vcc is powered with 5V
The Edge connector gets VSS = GNDVCC_IN = 3.3VOUT-ENABLE1 = 3.3V
the other Pins are connected like in the schematics described (GND to GND and LVDS data pins to differential lines towards my FPGA input).
I did not connect the LVDS data pins to my FPGA so far since there is an issue with the voltage like i described.
I did not change anything at all on the DC1945A except the jumper configurations to my described settings.
This is te measurement with 100Mhz, 200MSa/s Osci but with 1:10 measuring heads
What is the position of JP5? It does look like you have CMOS outputs coming out of the part, but since there are LVDS buffers you will need to be in LVDS mode. Make sure that SCK (JP5) is pulled high.
J5 is on position LVDS. I also measured the voltage on each pin without the jumper connection. The LVDS pin has 1.78V this pin has the label "1" in the schematic. pin "2" has 3.3V and "3" has 0V. This is a little bit confusing for me. why is there 3.3V on VDD pin? This pin should be 1.8V too. The datasheet of the ADC says that in default mode LVDS is selected. So I put the jumper off but it did not change anything.I measured the LVDS input on the ADC site (the inputs of the repeaters). There was the LVDS signal:
I guess there is an issue with the repeaters. They get 3.3V VDD like the schematic of the DC1945A shows. This is working. The Voltage regulators are fine, i measured VDD = OVDD = 1.78V and "+3.3V" is also at 3.28V. I measured the current of the digital units (135mA), which is also not surprising. so i guess the repeater are still alive and doing something. I measured all VCC and GND pins of the repeaters. Everything should be fine. I give them 3.3V for the enable input like it's required. Then i thought my adapter board eventually could have a connection to 3.3V on the LVDS pins so I also measured it but this is not the case. If I do not enable the repeater, they do nothing as well as the adc lvds outputs.
Do you have any idea what could cause such a behavior?
Thanks for your help!
So it looks like the ADC is outputting LVDS, but the buffers aren't? Is output enable (/OE) on the buffers high or low? It should be low. What is the termination at the FPGA or adapter board? It seems like all the power levels are ok. Can you program the part serially? Then you can use the test pattern.
The out enable is high. I looked it up in the truth table from the repeater's datasheet. The out enable isnt active low but the /oe which are defined to optionally invert the output driver of the repeater. However they are already Hard wired to low on the Dc1945a. If the out enable is low, the repeaters do not work at All.
The Adapter Board is Just a through put to my fpga which has an internal termination of 100ohms but i did not connect it so far. I'm measuring the data Pins in idle Mode.
Sadly i cant program the adc serial since There is no direct access to the data Inputs of the adc. There is an io Bank instead which is then going to the adc. So i would have to interface the io Bank via i2c and put a Software spi on it to program the adc in serial Mode.