Solved: DC1945A LVDS issue

I have a question about the DC1945A Evaluationboard. I use the DC1945A: LTC2185 and LTC6409 COMBO BOARD to interface it with my zynq7000 FPGA. I read the Datasheets about the components in detail but there is an issue, which i can't understand so far. The output of the LVDS drivers should have an maximum output swing of 400mV. I measured it with an 100Mhz, 200MSA/s oscilloscope and I saw the signal wave going from 0V to 3,3V. The drivers of my FPGA support LVDS_25 and TMDS standard but i thought the LVDS would have +-400mV with an offset voltage around 1,2V like the datasheets say. I wonder if there is an issue with the electronic.

My configurations are:

Program Mode: PAR (JP1)
Duty cycle stab.: EN (JP2)
SHDN: DIS (JP3)
NAP: EN (JP4)

My Clock is a 10 Mhz 3.3V oscillator used in single ended mode.
The I and Q Inputs are not connected.

AMP VCC is powered with 3,3V
Digital vcc is powered with 5V

The Edge connector gets
VSS = GND
VCC_IN = 3.3V
OUT-ENABLE1 = 3.3V

the other Pins are connected like in the schematics described (GND to GND and LVDS data pins to differential lines towards my FPGA input).

I did not connect the LVDS data pins to my FPGA so far since there is an issue with the voltage like i described.

I did not change anything at all on the DC1945A except the jumper configurations to my described settings.

Greetings,
Max



solved
[edited by: MaxiLaxi at 3:59 PM (GMT 0) on 15 Nov 2019]