AD9249 Evaluation Board: clock (CLK+) frequency issues

Hi everyone,

I have to develop a system that samples 36 voltages synchronously. I've decided to use 3 AD9249EVM. From what I understand, there is the possibility to provide an external clock signal or to use a 65MHz internal oscillator. The FPGA I use to collect data is a Xilinx Zynq-7000 SoC ZC702 Evaluation Kit. This FPGA is clocked at 200 MHz. Based on how I realize the sampling of data from the AD9249, the upper limit of the CLK+ frequency I can provide to the AD9249EVM is about 13MHz (due to the fact that by default the DCO+- signals are produced at 7 times the CLK+ frequency). Consequently the intention is to work with a CLK+ at around 10MHz.

Having seen that it is possible to connect an HSC-ADC-EVALEZ to acquire data, I would like to understand at which frequency this board works in order to manage the sampling data acquisition.

Is there the possibility of rescaling the 65MHz clock generated by the oscillator on the AD9249EVM at around 10 MHz?
If so, how can I carry out such rescaling? I guess I have to write to registers. In this case, should this be done every time I feed AD9249EVM? Or are the settings stored somewhere?

Does the CLK+ have to be a periodic signal? Let me explain: I would like to understand if we can provide a CLK+ made of square waves at a certain frequency that alternates with instants when the CLK+ goes to zero and then starts to change again as a square wave at 10MHz. Or must it be a simple square wave at a certain frequency (i.e. a purely periodic signal)?

Having to run 3 AD9249EVM synchronously, is it sufficient to supply the same CLK+ to all 3 boards? Or is it necessary to use the sync signal? I would like some clarification on the functions of this signal.

Finally I would like to ask if it is possible to have schematic/ manuals/datasheet of the version of the AD9249EVM with FMC connector since I can only find schematics and datasheet referred to the version with the tyco connector(60 pins).

Thanks,
Pietro



tagged
[edited by: JValeriani at 8:42 PM (GMT 0) on 16 Oct 2019]
  • The idea is to produce vhdl code that generates a periodic signal. This is not a clock generated by an oscillator but a signal that varies via an finite state machine. In practice it is like a data. These are LVCMOS25 outputs.

    As for the signals DCO1 + - and DCO2 + - I would like to understand what kind of relationship there is between these signals (and also between FCO1 + - and FCO2 + -).
    I would like to know if it is possible to use only the DCO1 + - and FCO1 + - to sample the data provided by all the ADCs on the board (both bank 1 and bank 2). In practice, to know if it is correct to consider equal the signals from the two banks and therefore to use only those of one bank.Or is it possible that sampling errors are introduced?

    Thanks,
    Pietro

  • 0
    •  Analog Employees 
    on Oct 18, 2019 5:39 PM over 1 year ago in reply to pietrom

    Hi Pietro,

    LVCMOS25 levels should be fine for applying to J802 of the AD9249 evaluation board. The AD9249 clock input has a wide range of valid levels. You might have to remove R808 and R803 (shunt resistors) on the AD9249 evaluation board if the levels are not high enough.

    Please note that clocks generated by an FPGA are typically noisy so ADC performance will likely suffer.

    Regarding the output clocks, as stated in the AD9249 datasheet, DCO±1 is used to capture the D±x1 (Bank 1) data; DCO±2 is used to capture the D±x2 (Bank 2) data. FCO±1 and FCO±2 signal the start of a new output byte, and the frequency is equal to the sample clock rate. FCO±1 frames the D±x1 (Bank 1) data; FCO±2 frames the D±x2 (Bank 2) data.

    If you choose to use DCO±1 to capture data from both Bank 1 and Bank 2, it could work much of the time, but there is high risk of capture errors.

    Thanks,

    Doug

  • The output of zynq is a signle ended lvcmos25 signal. This means that the clock I produce is a square wave that varies from 0V to 2.5V. Referring to the AD9249 datasheet, we read the following:
    CLK +, CLK− to GND: −0.3 V to +2.0 V
    This means that I have to reduce the width of my square wave. Right?

    "You might have to remove R808 and R803 (shunt resistors) on the AD9249 evaluation board if the levels are not high enough."
    By removing one or both, what do I get? How can I understand how the input voltage range varies?
    Could you better explain what to remove to get what?

    Could you also explain to me how to physically remove these resistors?

    What do you suggest among the following three options? Use a resistive divider on the signal from the zynq, remove shunt resistors, or use an IC to reduce the voltage level of the CLK +?

  • +1
    •  Analog Employees 
    on Oct 21, 2019 4:11 PM over 1 year ago in reply to pietrom

    Hi Pietro,

    That is good that you are taking care not to exceed the absolute maximum voltage rating of the clock pins. If you were applying the 2.5V peak-to-peak directly to the ADC clock pins, this would be a problem.

    On the AD9249 evaluation board, the single-ended 2.5V peak-to-peak clock signal will IDEALLY be converted to a 2.5V peak-to-peak differential signal by the clock transformer/balun. A 2.5V peak-to-peak differential signal means that each of the transformer/balun outputs would have a 1.25V peak-to-peak swing. With a common mode voltage of 0.9V, that means that the differential clock signals will swing from about 0.28V to 1.53V with respect to ground. These levels are OK for AD9249; they do not violate the absolute maximum voltage rating.

    By removing R808 (33Ohms) and R803 (33Ohms) you are reducing the load on your clock driver circuit. The clock circuit is designed to accommodate various types of clock sources. In the case where you are driving the AD9249 evaluation board clock input with a signal generator with 50Ohm source impedance, R808 and R803 together form a differential 66Ohm load, which looks more like 50Ohms when seen through the balun. Your LVCMOS25 driver likely is not meant to drive a 50Ohm load. In this case you should remove R808 and R803. You have to be willing to do some experimentation! Slight smile

    To remove the surface mount resistors you need to heat the solder connections. I use two soldering irons to simultaneously heat each side of the resistor, and then remove the resistor using the soldering iron tips. You could also heat the whole resistor with one soldering iron and remove the resistor with tweezers. You can try different ways to see what works for you.

    I think you should try applying your single-ended LVCMOS signal to J802 on the AD9249 evolution board before removing R808 and R803. Measure the amplitude of the clock signals close to the ADC to verify that the absolute maximum voltage rating is not exceeded.

    Thanks,

    Doug