AD9249 Evaluation Board: clock (CLK+) frequency issues

Hi everyone,

I have to develop a system that samples 36 voltages synchronously. I've decided to use 3 AD9249EVM. From what I understand, there is the possibility to provide an external clock signal or to use a 65MHz internal oscillator. The FPGA I use to collect data is a Xilinx Zynq-7000 SoC ZC702 Evaluation Kit. This FPGA is clocked at 200 MHz. Based on how I realize the sampling of data from the AD9249, the upper limit of the CLK+ frequency I can provide to the AD9249EVM is about 13MHz (due to the fact that by default the DCO+- signals are produced at 7 times the CLK+ frequency). Consequently the intention is to work with a CLK+ at around 10MHz.

Having seen that it is possible to connect an HSC-ADC-EVALEZ to acquire data, I would like to understand at which frequency this board works in order to manage the sampling data acquisition.

Is there the possibility of rescaling the 65MHz clock generated by the oscillator on the AD9249EVM at around 10 MHz?
If so, how can I carry out such rescaling? I guess I have to write to registers. In this case, should this be done every time I feed AD9249EVM? Or are the settings stored somewhere?

Does the CLK+ have to be a periodic signal? Let me explain: I would like to understand if we can provide a CLK+ made of square waves at a certain frequency that alternates with instants when the CLK+ goes to zero and then starts to change again as a square wave at 10MHz. Or must it be a simple square wave at a certain frequency (i.e. a purely periodic signal)?

Having to run 3 AD9249EVM synchronously, is it sufficient to supply the same CLK+ to all 3 boards? Or is it necessary to use the sync signal? I would like some clarification on the functions of this signal.

Finally I would like to ask if it is possible to have schematic/ manuals/datasheet of the version of the AD9249EVM with FMC connector since I can only find schematics and datasheet referred to the version with the tyco connector(60 pins).

Thanks,
Pietro



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[edited by: JValeriani at 8:42 PM (GMT 0) on 16 Oct 2019]
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  • 0
    •  Analog Employees 
    on Oct 15, 2019 5:12 PM

    Hi Pietro,

    Thank you for your interest in AD9249.

    • I do not know the technical details of the HSC-ADC-EVALEZ, but I believe it can capture data across the various sample rates of AD9249.
    • The AD9249 has a clock (frequency) divider, which can divide the clock frequency by integers of 2 through 8. The clock frequency divider is configured by Register 0x0B Bits[2:0]. The minimum sample rate of AD9249 is 10Msps, so 65M/8 = 8.125 is too low. 65M/6 = 10.8333M would be OK.
      • As long as the AD9249 remains powered up, it will retain its register settings. Doing a Digital Reset using Register 0x08 also does not disturb register contents.
      • The settings are not otherwise stored anywhere. If the AD9249 is powered-down, previous register settings will be lost.
    • Yes, the clock should be a steady state periodic signal. In cases where it is not periodic, there is risk of not starting back up cleanly and thus disturbing the state of the ADC. In that case a Digital Reset (Register 0x08) is needed. See the CLOCK STABILITY CONSIDERATIONS section of the datasheet.
    • If you are not using the clock frequency divider, then it is sufficient to supply the same clock to all 3 boards. If you use the clock frequency divider then you need to use the SYNC signal to ensure that the dividers in all the AD9249s are in the same state.
      • If you apply a lower frequency clock to the AD9249 and use divide-by-1 (default), then you do not need to use the SYNC signal to synchronize all the ADCs.
    • The schematics for the FMC version of the AD9249 are on the Wiki QuickStart page https://wiki.analog.com/resources/eval/ad9249-65ebz . Please let me know if you have any trouble finding them. We are in the process of updating the pictures. The content is relevant to the FMC board.

    Thank you.

    Doug

  • hi 

    I have some question , in the data sheet of AD9249 ,there is a register 0x100 ,i can use it to choose sample rate,right ? As it shows , only 20 msps .40 msps, 50 msps, 65msps can be selected. Why did you say "The minimum sample rate of AD9249 is 10Msps " , why did you say  "10.8333M would be ok " ?  Thank you very much

  • 0
    •  Analog Employees 
    on Mar 11, 2021 6:18 AM in reply to 1291904192@QQ.COM

    Hi,

    I'm sorry about the confusion.

    As stated in Table 4 of the AD9249 datasheet, the minimum sample rate of AD9249 is 10Msps, so 10.8333M is above the minimum and so it is OK.

    Register 0x100 sets AD9249 into lower power states with new maximum (not minimum) sample rate limits. In all Register 0x100 settings, the minimum sample rate is still 10Msps.

    Thank you.

    Doug

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  • 0
    •  Analog Employees 
    on Mar 11, 2021 6:18 AM in reply to 1291904192@QQ.COM

    Hi,

    I'm sorry about the confusion.

    As stated in Table 4 of the AD9249 datasheet, the minimum sample rate of AD9249 is 10Msps, so 10.8333M is above the minimum and so it is OK.

    Register 0x100 sets AD9249 into lower power states with new maximum (not minimum) sample rate limits. In all Register 0x100 settings, the minimum sample rate is still 10Msps.

    Thank you.

    Doug

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