AD9249 Evaluation Board: clock (CLK+) frequency issues

Hi everyone,

I have to develop a system that samples 36 voltages synchronously. I've decided to use 3 AD9249EVM. From what I understand, there is the possibility to provide an external clock signal or to use a 65MHz internal oscillator. The FPGA I use to collect data is a Xilinx Zynq-7000 SoC ZC702 Evaluation Kit. This FPGA is clocked at 200 MHz. Based on how I realize the sampling of data from the AD9249, the upper limit of the CLK+ frequency I can provide to the AD9249EVM is about 13MHz (due to the fact that by default the DCO+- signals are produced at 7 times the CLK+ frequency). Consequently the intention is to work with a CLK+ at around 10MHz.

Having seen that it is possible to connect an HSC-ADC-EVALEZ to acquire data, I would like to understand at which frequency this board works in order to manage the sampling data acquisition.

Is there the possibility of rescaling the 65MHz clock generated by the oscillator on the AD9249EVM at around 10 MHz?
If so, how can I carry out such rescaling? I guess I have to write to registers. In this case, should this be done every time I feed AD9249EVM? Or are the settings stored somewhere?

Does the CLK+ have to be a periodic signal? Let me explain: I would like to understand if we can provide a CLK+ made of square waves at a certain frequency that alternates with instants when the CLK+ goes to zero and then starts to change again as a square wave at 10MHz. Or must it be a simple square wave at a certain frequency (i.e. a purely periodic signal)?

Having to run 3 AD9249EVM synchronously, is it sufficient to supply the same CLK+ to all 3 boards? Or is it necessary to use the sync signal? I would like some clarification on the functions of this signal.

Finally I would like to ask if it is possible to have schematic/ manuals/datasheet of the version of the AD9249EVM with FMC connector since I can only find schematics and datasheet referred to the version with the tyco connector(60 pins).

Thanks,
Pietro



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[edited by: JValeriani at 8:42 PM (GMT 0) on 16 Oct 2019]