I have to develop a system that samples 36 voltages synchronously. I've decided to use 3 AD9249EVM. From what I understand, there is the possibility to provide an external clock signal or to use a 65MHz internal oscillator. The FPGA I use to collect data is a Xilinx Zynq-7000 SoC ZC702 Evaluation Kit. This FPGA is clocked at 200 MHz. Based on how I realize the sampling of data from the AD9249, the upper limit of the CLK+ frequency I can provide to the AD9249EVM is about 13MHz (due to the fact that by default the DCO+- signals are produced at 7 times the CLK+ frequency). Consequently the intention is to work with a CLK+ at around 10MHz.
Having seen that it is possible to connect an HSC-ADC-EVALEZ to acquire data, I would like to understand at which frequency this board works in order to manage the sampling data acquisition.
Is there the possibility of rescaling the 65MHz clock generated by the oscillator on the AD9249EVM at around 10 MHz? If so, how can I carry out such rescaling? I guess I have to write to registers. In this case, should this be done every time I feed AD9249EVM? Or are the settings stored somewhere?
Does the CLK+ have to be a periodic signal? Let me explain: I would like to understand if we can provide a CLK+ made of square waves at a certain frequency that alternates with instants when the CLK+ goes to zero and then starts to change again as a square wave at 10MHz. Or must it be a simple square wave at a certain frequency (i.e. a purely periodic signal)?
Having to run 3 AD9249EVM synchronously, is it sufficient to supply the same CLK+ to all 3 boards? Or is it necessary to use the sync signal? I would like some clarification on the functions of this signal.
Finally I would like to ask if it is possible to have schematic/ manuals/datasheet of the version of the AD9249EVM with FMC connector since I can only find schematics and datasheet referred to the version with the tyco connector(60 pins).
As for the divider, what can I get from this circuit? If I connect an external clock to the CLK +, can I reduce or increase the frequency of this clok? If I understand correctly one can only increase the frequency (in fact with the 65 MHz you can divide the period and get signals with frequency up to 8 times: 520MHz).
Thank you for your interest in AD9249.
The AD9249 clock frequency divider can only reduce the ADC sample rate assuming a given clock frequency.
Your example scenario is correct, If you wanted to apply a 520MHz clock to AD9249, you would need to set the clock frequency divider to divide-by-8 thus resulting in a sample rate of 520M/8 = 65Msps.
The function of the clock divider is not clear from the two previous answers. From what I understand I can use it to get, starting from the 65MHz clock, a signal up to 520MHz. From your answer, however, I do not understand if I can increase or reduce this frequency.Because I'm interested in understanding if I can use the 65MHz signal to get one at around 10MHz.
1) "The AD9249 has a clock (frequency) divider, which can divide the clock frequency by integers of 2 through 8. The clock frequency divider is configured by Register 0x0B Bits [2: 0]. The minimum sample rate of AD9249 is 10Msps , so 65M / 8 = 8.125 is too low. 65M / 6 = 10.8333M would be OK. "
2) "Your example scenario is correct, If you wanted to apply at 520MHz clock to AD9249, you would need to set the clock frequency divide-by-8 thus resulting in a sample rate of 520M / 8 = 65Msps."
From the answer 1 it seems that a frequency lower than 65MHz can be obtained, from the 2 that one can increase this frequency.I think that only one of the two possibilities is the right one.Could you be clearer? Thank you so much.
Referring to the 'clock input options' section of the datasheet:"The AD9249 has a flexible clock input structure. The clock input can be to CMOS, LVDS, LVPECL, or sine wave signal." Moreover in the absolute maximum ratings section the clk can accept signals in the range from -0.3V to 2.0V.My intention is to produce a periodic signal (at 10MHz) generated by circuits made in VHDL on the zynq and connect this signal to an SMA so as to connect it to the CLK + of the board. How can I know if this signal is suitable for driving the ADC? I refer mainly to electrical levels. Can you give me some clarification regarding the CMOS and LVDS levels and all the other conditions that my clock signal must satisfy?
Can you confirm that the CLK + signal is always sufficient? (in fact from the schematic it seems that the SMA connector for the CLK- is not even mounted). Or is it valid only in some situations?For example, in the case of a lvds clk, is it sufficient to connect the two pins from which I produce the 10MHz CLK + to an SMA connector and connect this to the AD9249 board?Thanks,Pietro
Let's define some terms.
Clock frequency is the frequency of the clock signal from your signal generator.
Sample rate is the rate at which the ADC samples the analog input.
Clock frequency and sample rate are related.
Please read your #1 and #2 again. They are both correct.
If you are going to apply a 10MHz clock signal you must use the divide-by-1 setting of the clock frequency divider. Divide-by-1 is the default value so you do not need to do any SPI configuration for this.
The AD9249 evaluation board uses a balun to convert a single ended clock signal to differential, so the AD9249 receives a differential clock signal.
What voltage levels is your clock generator capable of driving, into what kind of load?