AD9637 DC shift at different clock frequencies

Hello,

I am using the AD9637BCPZ-80.

I have to shift the VCM down ~ neg 0.9VDC in order to accommodate a positive gaussian pulse of ~2V p-p amplitude. 

The CLK +/- pins for the AD are driven by the LTC6950 PLL set to 8x the input clock (AC coupled).

I have to select from a clk oscillator running at 10MHZ or an external clock that runs at 9.37MHZ. These are both selected inputs to the PLL.

I confirmed that at the output of the PLL that I do have an 80MHZ local clk (10MHZ * 8) and a 75MHZ external clock (9.37MHZ * 8 = 94.96MHZ)

The VREF is Internal.

Digital Reset at reg 0x08 is invoked at power-up and after each clk change.

However, depending on what clk I select, I see a shift in the baseline (pedestal) of ~75 ADC counts.

The attached image is a plot that shows the same 1V p-p pulse taken with the 10MHZ clk and the 9.37MHZ clk. 

Thank you,



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[edited by: JValeriani at 7:40 PM (GMT 0) on 9 Oct 2019]
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  • 0
    •  Analog Employees 
    on Oct 8, 2019 11:57 PM

    Hi TimCam,

    Thank you for using the AD9637 on your project. Thanks for doing the Digital Reset after every clock change. That gives us a good starting point.

    Would you please explain more about your input signal and how you are applying it to the ADC inputs? If the input common mode voltage is really negative 0.9V, that is outside the valid range for AD9637. Are you driving the inputs differentially? Are you DC coupling to the inputs? How is the input common mode voltage being applied? Are you able to share the input portion of your schematics?

    Thank you.

    Doug

  • Hi Doug,

    I attached the signal conditioning circuit (input buffer) with the ADC circuit PDF.

    I am using the AD8130 for the input signal, DC coupled.

    Here I shift the input down to just above 0.9VDC. I set the VOFFSET to ~ -870mv so I have a little headroom above the floor.

    Then the LTC6403 is used to convert the 8130 single ended output to differential with a shifted baseline. It is also used as a filter.

    Thanks,

    Tim

    PDF

  • 0
    •  Analog Employees 
    on Oct 21, 2019 11:06 PM in reply to timcam

    Hi Tim,

    I don't believe that the reactive portion of the input impedance changes as a function of sample rate, but of course I could be wrong.

    Thinking aloud, some things that change as the sample rate changes are:

    • The DC load on the input common mode
    • There is less time between sampling instants for the inputs to settle

    Increasing the difference between your two sample rates is something I was thinking about to see if the DC common mode load is somehow affecting this.

    Regarding the input settling, on our evaluation board we usually have series resistors between the transformer/balun and the ADC inputs, to dampen switched cap transients. As an experiment, could you try replacing your series inductors with resistors (say, 33Ohms)?

    Thanks for your patience, and doing these tests.

    Doug

  • Hi Doug,

    I made a table of results sweeping the sampling rate from 9.2MHZ to 10MHZ. It looks like when I am on the lower and higher ends, that we have the largest difference. 

    The series inductors are replaced with 330 ohms. This seems to provide more consistent p-p value.

    Freq. MHZ

    Base (ADC Count)

    Peak (ADC Count)

    p-p ADC Count

    9.2

    29

    439

    410

    9.3

    43

    451

    408

    9.4

    48

    453

    405

    9.5

    52

    456

    404

    9.6

    52

    457

    405

    9.7

    54

    459

    405

    9.8

    53

    458

    405

    9.9

    44

    454

    410

    10.0

    20

    431

    411

    Thanks,

    Tim

  • 0
    •  Analog Employees 
    on Nov 6, 2019 4:11 PM in reply to timcam

    Hi Tim,

    Thank you for the information. You mention a sample rate of 9.2MHz to 10MHz. This is the reference frequency to your PLL, correct? The ADC clock frequency is 8X the reference frequency, correct?

    The peak-to-peak code swing of your pulse ranges from 404 codes to 411 codes, so the difference is 7 codes.

    In the case of the PLL reference frequency being 9.4MHz, the pulse amplitude is 405 codes. With the PLL reference frequency of 10MHz the pulse amplitude is 411 codes. The difference is 6 codes.

    When you measured the outputs of the LTC6403 with reference frequency of 9.37MHz (close to 9.4MHz mentioned above) compared to 10MHz, you saw a difference of 2.6mV, which is about 5 codes.

    It seems to me that the difference in the LTC6403 output at different ADC sample rates accounts for the difference you are seeing in the ADC output code swing.

    Is it possible for you to investigate why the LTC6403 output changes when the ADC sample clock frequency changes?

    Regarding the value of the resistors to replace the inductors, I was thinking closer to 33 Ohms rather than 330 Ohms. If 330 Ohms is working then great. You have the freedom to try different values if needed.

    Thanks,

    Doug

  • Hi Doug,

    After testing the ADC boards in our system. The small variations in ADC counts are acceptable. Adding more decoupling with the 330 Ohm resistors to the ADC inputs greatly improved the variations in ADC counts.

    Thanks again for all your great help with this.

    Regards,

    Tim

  • 0
    •  Analog Employees 
    on Feb 4, 2020 5:00 PM in reply to timcam

    Hi Tim,

    Thank you very much for reporting back regarding this. Great job in experimenting and finding a solution.

    I hope your project is a great success.

    Doug

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