I am using the AD9637BCPZ-80.
I have to shift the VCM down ~ neg 0.9VDC in order to accommodate a positive gaussian pulse of ~2V p-p amplitude.
The CLK +/- pins for the AD are driven by the LTC6950 PLL set to 8x the input clock (AC coupled).
I have to select from a clk oscillator running at 10MHZ or an external clock that runs at 9.37MHZ. These are both selected inputs to the PLL.
I confirmed that at the output of the PLL that I do have an 80MHZ local clk (10MHZ * 8) and a 75MHZ external clock (9.37MHZ * 8 = 94.96MHZ)
The VREF is Internal.
Digital Reset at reg 0x08 is invoked at power-up and after each clk change.
However, depending on what clk I select, I see a shift in the baseline (pedestal) of ~75 ADC counts.
The attached image is a plot that shows the same 1V p-p pulse taken with the 10MHZ clk and the 9.37MHZ clk.
[edited by: JValeriani at 7:40 PM (GMT 0) on 9 Oct 2019]