AD9637 DC shift at different clock frequencies

Hello,

I am using the AD9637BCPZ-80.

I have to shift the VCM down ~ neg 0.9VDC in order to accommodate a positive gaussian pulse of ~2V p-p amplitude. 

The CLK +/- pins for the AD are driven by the LTC6950 PLL set to 8x the input clock (AC coupled).

I have to select from a clk oscillator running at 10MHZ or an external clock that runs at 9.37MHZ. These are both selected inputs to the PLL.

I confirmed that at the output of the PLL that I do have an 80MHZ local clk (10MHZ * 8) and a 75MHZ external clock (9.37MHZ * 8 = 94.96MHZ)

The VREF is Internal.

Digital Reset at reg 0x08 is invoked at power-up and after each clk change.

However, depending on what clk I select, I see a shift in the baseline (pedestal) of ~75 ADC counts.

The attached image is a plot that shows the same 1V p-p pulse taken with the 10MHZ clk and the 9.37MHZ clk. 

Thank you,



tagged
[edited by: JValeriani at 7:40 PM (GMT 0) on 9 Oct 2019]
  • 0
    •  Analog Employees 
    on Oct 8, 2019 11:57 PM over 1 year ago

    Hi TimCam,

    Thank you for using the AD9637 on your project. Thanks for doing the Digital Reset after every clock change. That gives us a good starting point.

    Would you please explain more about your input signal and how you are applying it to the ADC inputs? If the input common mode voltage is really negative 0.9V, that is outside the valid range for AD9637. Are you driving the inputs differentially? Are you DC coupling to the inputs? How is the input common mode voltage being applied? Are you able to share the input portion of your schematics?

    Thank you.

    Doug

  • Hi Doug,

    I attached the signal conditioning circuit (input buffer) with the ADC circuit PDF.

    I am using the AD8130 for the input signal, DC coupled.

    Here I shift the input down to just above 0.9VDC. I set the VOFFSET to ~ -870mv so I have a little headroom above the floor.

    Then the LTC6403 is used to convert the 8130 single ended output to differential with a shifted baseline. It is also used as a filter.

    Thanks,

    Tim

    PDF

  • 0
    •  Analog Employees 
    on Oct 9, 2019 4:49 PM over 1 year ago in reply to timcam

    Hi Tim,

    Thanks for the schematics. I've asked the LTC6403 experts to have a look at the amplifier portion.

    I see that the VOCM pin of the LTC6403 is 1.1V. Does the following represent what is being applied to the ADC inputs?

    Thank you.

    Doug

  • Hi Doug,

    Yes, this is exactly what I have at the input to the ADC.

    Thanks,

    Tim

  • 0
    •  Analog Employees 
    on Oct 10, 2019 1:12 AM over 1 year ago in reply to timcam

    Hi Tim,

    From what I can see, the AD9637 should have no problem with this signal. The colors on your screenshot even match the ones on my graph! Slight smile

    Would you please confirm regarding the clock frequencies? The two sample rates you are comparing are 80Msps and 75Msps, correct? The 10MHz and 9.37MHz are reference clocks for the PLL, correct?

    How is the 94.96MHz clock used?

    Thanks,

    Doug