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[AD9262] ADC Stop during operation

Thanks in advance for my question.
I use the AD9262.
Use according to the guidelines (Table 9.).
The chip ID reads 0x22 well through SPI, and the value I set is well written and read.
CLK uses 52MHz, MUX uses 25, and KMOD uses 13 to generate a DCO of about 100MHz.
The input signal (Tone, 1MHz, -20dBm) is applied to capture well.
However, the ADC chip is reset at some point during input signal removal or operation.
Why does this happen?
Attach the picture of normal operation and picture of reset operation when removing signal.
Please help me.

[normal register read]                                [normal signal capture]

[remove signal (VIn), reset resigster]          [remove signal (VIn), signal capture]

  • Hello,

    Reading through is not apparent why the device would issue a chip RESET that would set all the SPI settings to default start up value if one removes the signal input or injects a signal causing overload. 

    The only thing that could be causing a RESET is if a hardware RESET is issued via PIN 50 of device or a software RESET is used using 0x00 (bit 5 or 2).   If RESET pin is not connected..........suggest that you tie low since it is not clear on datasheet if pin has internal pull-down resistor.

  • Thank you for answer.
    Pin 50 of the chip is connected to the FPGA.
    While testing, I found one more symptom.
    Connect one of channel A (or B) to GND.
    This will solve the problem.
    Although two channels cannot be used, one channel will operate normally when one channel is connected to GND. (No reset issue)
    What do you think about this condition?