I just started working on a project for driving a multiphase motor. The idea would be to use two AD9249 evm to sample the conditioned signals of the motor phase currents. We want the converters to communicate with a zynq702.Do you confirm that I can have the two cards sampled at the same time by supplying the same sync signal?As for communication: I am not very confident with communication in general and in particular with spi. It is not clear to me how to communicate with the two boards to get the various samples. I read both the datsheet of the AD9249 and the AN877-application note but I can't find out which are the registers in which the samples of each adc are saved. I would also like to know if you can read all sixteen channels in a row with a single command. In short, I would like help on the above and any clarification / advice for the system that you want to implement.thanks
Thank you for your interest in AD9249.
There are more resources on analog.com that explain more about ADCs. Please let me know if you are interested in any of these.
So for sampling management is it sufficient to supply the CLK + and CLK- signals to the various boards? What is the synq signal for?To get data on zynq at the exact moment do I have to use the DCO and FCO signals?Regarding the frequency of the DCO signals, by default, this corresponds to 7 times that of the CLK + -, right? Acting on register 0x0B (clock divide) what does it change? increase or decrease the frequency of which signals?Regarding the other resources, I accept any suggestions on material that may be useful for my project.
Thank you so much
And also, is it possible to connect the various ADCs with each other and take a single pin as a reference (to be connected to the ground of the zynq)? I ask because the number of pins available is limited and I don't have enough pins to connect all the differential outputs of the two boards.
Yes, if you do not use the AD9249 clock frequency divider (Register 0x0B) then it is sufficient to supply the same clock signal to each AD9249. The SYNC signal is used to reset and synchronize the clock frequency dividers when other than divide-by-1 is used.
Yes, you need to use the DCO and FCO signals. DCO±1 is used to capture the D±x1 (Bank 1) data; DCO±2 is used to capture the D±x2 (Bank 2) data. FCO±1 and FCO±2 signal the start of a new output byte, and the frequency is equal to the sample clock rate.
The frequency of DCO is 7X the clock frequency in default mode.
Register 0x0B sets the value of the clock frequency divider. In the default configuration Register 0x0B = 0x00 which means that the clock frequency is divided by 1. You apply a 65MHz clock and the ADC samples at 65Msps.
If for example you have only a 130MHz clock available in your system and you want to use this clock for AD9249, then you would set Register 0x0B = 0x0x01 (divide-by-2). The applied 130MHz clock would be divided by 2 within the AD9249 and the AD9249 would operate at 130MHz/2 = 65Msps. When the clock frequency divider is used and if you need to synchronize multiple devices, then the SYNC signal must be used.
This is a good general reference on data converters: https://www.analog.com/en/education/education-library/data-conversion-handbook.html . It is a little old but the conceptual information is still valid. This information is not specific to the AD9249, but general ADC information.
Would you please explain more about what you mean by "connect the various ADCs with each other and take a single pin as a reference"? Because you mention differential outputs are you talking about using one DCO for several ADCs?
I give an example.the zynq is equipped with a fmc connector. If I had to use two AD9249 boards I would have 32 adc available. since each output is a differential signal I should connect 64 cables to the zynq. I would therefore like to know if there is the possibility of reducing the number of connections with the zynq. All this by connecting one of the two outputs of each adc to each other and using this pin as a common reference for all ADCs. In this way I would have 33 connections. Obviously all ADCs are configured in the same way.In short, I would like to know if there is a way to reduce the number of connections from the output of the AD9249 to the zynq.
It sounds like you would like to use the "+" outputs for data transmission and tie the "-" outputs together. Both the "+" and "-" outputs source and sink current and so both connections are needed to transmit data. LVDS drivers by definition are differential. Each output lane needs to have both connections to actively force a logic 1 or logic 0 across the termination resistor. AN-586 on analog.com explains more about LVDS outputs.
On the FPGA side I'm sure the LVDS receivers also need a differential connection.
So, if I am understanding you correctly, I do not believe that your proposed solution will work.
With serial LVDS you are already getting the advantage of having only one output lane per channel. If the ADC had a fully parallel output, you would need 14 data lanes for each channel.
FYI ADCs with JESD204B outputs have the ability to output multiple channels onto one lane, plus JESD204B eliminates the clock pins. Unfortunately as far as I know we do not have any 16 channel ADCs with JESD204B outputs.