As shown in the above figure,Read the register for AD9633,
The number read out should be 0x60, but the actual number read out is 0x63. What causes this?
AD9633
Recommended for New Designs
The AD9633 is a quad, 12-bit, 80 MSPS/105 MSPS/125 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost...
Datasheet
AD9633 on Analog.com
As shown in the above figure,Read the register for AD9633,
The number read out should be 0x60, but the actual number read out is 0x63. What causes this?
Thanks for your patient to answer my questions! and i have more new problems!
As shown in the above right figure.The signal FCO,its frequency is lower than DCO,but in fact,The Fco frequency of FCO signal is higher than DCO from signalTap. I have carefully checked the circuit diagram and quartus pin distribution diagram, and they are all correct. Why does this waveform appear?
Thanks for your patient to answer my questions! and i have more new problems!
As shown in the above right figure.The signal FCO,its frequency is lower than DCO,but in fact,The Fco frequency of FCO signal is higher than DCO from signalTap. I have carefully checked the circuit diagram and quartus pin distribution diagram, and they are all correct. Why does this waveform appear?
FCO should have six bits of data in one cycle, but why do I have eight bits in every cycle?
Hi,
I have no explanation why you see FCO having a higher frequency than DCO. That seems impossible to me but you checked the connections. All I can say is to please double check the connections again.
Doug
Hi Xmarcus724,
Would you please expand the timing diagram to fully include the clock signal. From what I can see it looks to be quite far off from being 50% duty cycle.
Thank you.
Doug