SPI of AD9633

Hi Xmarcus724,

I'm sorry for the slow response. I'll try to look at your question within the next day or so.

Doug

Hi Xmarcus724,

0x63 is the correct value when reading Register 0x02 of AD9633-125. The only bits defined for Register 0x02 are Bits[6:4]. For the 125Msps speed grade, Register 0x02 Bits[6:4] = 6, which is what you are seeing. Bits[3:0] are not defined in the datasheet but 0x3 is the correct value for these bits.

So, you are reading correctly. Thank you.

Doug

Thanks for your patient to answer my questions! and i have more new problems!

As shown in the above right figure.The signal FCO,its frequency is lower than DCO,but in fact,The Fco frequency of FCO signal is higher than DCO from signalTap. I have carefully checked the circuit diagram and quartus pin distribution diagram, and they are all correct. Why does this waveform appear?

FCO should have six bits of data in one cycle, but why do I have eight bits in every cycle？

Hi,

I have no explanation why you see FCO having a higher frequency than DCO. That seems impossible to me but you checked the connections. All I can say is to please double check the connections again.

Doug

Hi Xmarcus724,

Would you please expand the timing diagram to fully include the clock signal. From what I can see it looks to be quite far off from being 50% duty cycle.

Thank you.

Doug