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DC2226A Reference design gives no results

i have LTC DC2226A ADC-Board, DC2159A Interface-Board and KC705.

WIth FPGA Reference design on KC705 and linear Lab Tools on PC It is not possible to get results.

I changed nothing on sourcecode, and it is running perfect, communication OK. But there is no result data, all 4 channels deliver no data.

Hier ist output of communication:

LTC2123 DC2226 dual clocking solution Interface Program
Run number: 1

Runs with errors: 0

***********************************
Bitfile ID is 0xC0
All good!!
***********************************

Configuring ADCs over SPI:
ADC 0 configuration:
LTC2124 Register Dump:
Register 1: 0x00
Register 2: 0x00
Register 3: 0xF7
Register 4: 0x06
Register 5: 0x00
Register 6: 0x07
Register 7: 0x00
Register 8: 0x00
Register 9: 0x00
Register A: 0x01
Configuring ADCs over SPI:
ADC 1 configuration:
LTC2124 Register Dump:
Register 1: 0x00
Register 2: 0x00
Register 3: 0xD5
Register 4: 0x06
Register 5: 0x00
Register 6: 0x07
Register 7: 0x00
Register 8: 0x00
Register 9: 0x00
Register A: 0x01
Configuring clock generators over SPI:
Configuring LTC6954 (REF distribution)
SYNC LTC6954 Outputs
Configuring U10 (LTC6951): FPGA CLK, ADC2 Clock & SYSREF
Configuring U13 (LTC6951): FPGA SYSREF, ADC1 Clock and SYSREF
SYNC LTC6951 Outputs
Configuring LTC6954: Force OUT2- LOW
Reading Clock Status register; should be 0x16 (or at least 0x04 bit set)
Register 6 (Clock status): 0x000E
Configuring V6 JESD204B core!!
Configuring clock generators over SPI:
Configuring U10 (LTC6951): MUTE ADC2 SYSREF
Configuring U13 (LTC6951): MUTE FPGA SYSREF, ADC1 SYSREF
Capturing data and resetting...
Reading Clock Status register; should be 0x16 (or at least 0x04 bit set)
Register 6 (Clock status): 0x001E
Reading capture status, should be 0xF0 or 0xF4 (CH0, CH1, CH2, CH3 valid, Capture NOT done, data not fetched)
And it is... 0x00F4
Reading capture status, should be 0xF1 (CH0, CH1, CH2, CH3 valid, Capture IS done, data not fetched)
And it is... 0x00F1
Read out 0 samples for CH0, 1
Reading capture status, should be 0xF1 (CH0, CH1, CH2, CH3 valid, Capture IS done, data not fetched)
And it is... 0x00F1
Read out 0 samples for CH2, 3
0x0000, 0x0000, 0x0000, 0x0000
0x0000, 0x0000, 0x0000, 0x0000
0x0000, 0x0000, 0x0000, 0x0000
0x0000, 0x0000, 0x0000, 0x0000
0x0000, 0x0000, 0x0000, 0x0000
0x0000, 0x0000, 0x0000, 0x0000
0x0000, 0x0000, 0x0000, 0x0000
0x0000, 0x0000, 0x0000, 0x0000
0x0000, 0x0000, 0x0000, 0x0000
0x0000, 0x0000, 0x0000, 0x0000
0x0000, 0x0000, 0x0000, 0x0000
0x0000, 0x0000, 0x0000, 0x0000
0x0000, 0x0000, 0x0000, 0x0000
0x0000, 0x0000, 0x0000, 0x0000
0x0000, 0x0000, 0x0000, 0x0000
0x0000, 0x0000, 0x0000, 0x0000


C:/llt/demo_board_examples/ltc21xx/ltc2123/ltc2123_dc2226_dual_clocking_solution.py:282: RuntimeWarning: divide by zero encountered in log10
freq_domain_magnitude_db_ch0 = 20 * np.log10(freq_domain_magnitude_ch0/fftlength)
C:/llt/demo_board_examples/ltc21xx/ltc2123/ltc2123_dc2226_dual_clocking_solution.py:287: RuntimeWarning: divide by zero encountered in log10
freq_domain_magnitude_db_ch1 = 20 * np.log10(freq_domain_magnitude_ch1/fftlength)
C:/llt/demo_board_examples/ltc21xx/ltc2123/ltc2123_dc2226_dual_clocking_solution.py:292: RuntimeWarning: divide by zero encountered in log10
freq_domain_magnitude_db_ch2 = 20 * np.log10(freq_domain_magnitude_ch2/fftlength)
C:/llt/demo_board_examples/ltc21xx/ltc2123/ltc2123_dc2226_dual_clocking_solution.py:297: RuntimeWarning: divide by zero encountered in log10
freq_domain_magnitude_db_ch3 = 20 * np.log10(freq_domain_magnitude_ch3/fftlength)


Found peaks in these bins:
5
5
5
5
with these phases:
0.0
0.0
0.0
0.0

JEDEC core config registers:
Version: 06 00 00 00
Reset: 00 00 00 00
ILA Support: 00 00 00 01
Scrambling: 00 00 00 00
SYSREF Handling: 00 00 00 01
Reserved...: 00 00 00 00
Test Modes: 00 00 00 00
Link err stat, 0-7: 00 00 00 00
Octets/frame: 00 00 00 01
frames/multiframe(K): 00 00 00 0F
Lanes in Use: 00 00 00 03
Subclass: 00 00 00 01
RX buf delay: 00 00 00 00
Error reporting: 00 00 00 00
SYNC Status: 00 01 00 01
Link err stat, 8-11: 00 00 00 00

ILAS and stuff for lane 0:
ILA config Data 0: 00 00 01 01
ILA config Data 1: 00 00 00 01
ILA config Data 2: 00 00 00 0F
ILA config Data 3: 01 00 0C EF
ILA config Data 4: 01 0F 0D 01
ILA config Data 5: 00 00 00 00
ILA config Data 6: 00 2C 00 00
ILA config Data 7: 00 00 00 00
Test Mode Err cnt: 00 00 00 00
Link Err cnt: 00 00 00 00
Test Mode ILA cnt: 00 00 00 00
Tst Mde multif. cnt: 00 00 00 00
Buffer Adjust: 00 00 00 14

ILAS and stuff for lane 1:
ILA config Data 0: 00 00 01 01
ILA config Data 1: 00 00 00 01
ILA config Data 2: 00 00 00 0F
ILA config Data 3: 01 01 0C EF
ILA config Data 4: 01 0F 0D 01
ILA config Data 5: 00 00 00 00
ILA config Data 6: 00 2D 00 00
ILA config Data 7: 00 00 00 00
Test Mode Err cnt: 00 00 00 00
Link Err cnt: 00 00 00 00
Test Mode ILA cnt: 00 00 00 00
Tst Mde multif. cnt: 00 00 00 00
Buffer Adjust: 00 00 00 10

ILAS and stuff for lane 2:
ILA config Data 0: 00 00 01 01
ILA config Data 1: 00 00 00 01
ILA config Data 2: 00 00 00 0F
ILA config Data 3: 01 00 0C AB
ILA config Data 4: 01 0F 0D 01
ILA config Data 5: 00 00 00 00
ILA config Data 6: 00 E8 00 00
ILA config Data 7: 00 00 00 00
Test Mode Err cnt: 00 00 00 00
Link Err cnt: 00 00 00 00
Test Mode ILA cnt: 00 00 00 00
Tst Mde multif. cnt: 00 00 00 00
Buffer Adjust: 00 00 00 14

ILAS and stuff for lane 3:
ILA config Data 0: 00 00 01 01
ILA config Data 1: 00 00 00 01
ILA config Data 2: 00 00 00 0F
ILA config Data 3: 01 01 0C AB
ILA config Data 4: 01 0F 0D 01
ILA config Data 5: 00 00 00 00
ILA config Data 6: 00 E9 00 00
ILA config Data 7: 00 00 00 00
Test Mode Err cnt: 00 00 00 00
Link Err cnt: 00 00 00 00
Test Mode ILA cnt: 00 00 00 00
Tst Mde multif. cnt: 00 00 00 00
Buffer Adjust: 00 00 00 10