My customer is planning to employ LTC2153-14. Here are my customer question.
(I don't have demoboard now. please tell me.)
Q1)Input CLK signal to ENC PIN after power-on. We would like to know the CLKOUT PIN condition.
What Is the default condition? Can we see phase shift "0" degree CLKOUT or No COLKOUT?
If, No CLKOUT, Do we need to set up "REGISTER A2: TIMING REGISTER (ADDRESS 02h)" ?
Q2)What happens if the program "REGISTER A2: TIMING REGISTER (ADDRESS 02h)" is changed during the operation of the CLK output?
Is there "Glitch Noise" generated on CLKOUT PIN?
The CLKOUT will follow the ENC signal with a small delay. If ENC is high then CLKOUT will be high shortly after that.
The default it 0 degree phase shift
There is no reason to dynamically change the phase of the output clock. It is something you set at the beginning of the data collection and leave it alone. If you were to switch it dynamically what would happen would depend on what your data collection engine is doing in the FPGA. It would take some clock cycles to regain sync.
Thank you very much for your prompt reply!
I will try to discuss my customer with your reply on Mnday.