I need to modify the AD9694-500EBZ embedded software on the ADS7-V2EBZ FPGA to meet our system requirements. An example source Code is posted on EZ (this). I am not sure the provided source code in the post belongs to the old or new AD9694-500EBZ boards (as referred to in Wiki) and appreciate if you can clarify it.
yes, same hdl for both version of boards
it is the same. no separate hdl is necessary.
Do you mean the source code is the same as the code currently running on the new AD9694-500EBZ eval board?
UmeshJ, Thanks a lot.
Vivado 18 and 19, both trigger error message about the unknown FIFO and DDR1 IP cores. Please see the screen shot below.
Could you please let me know how I can work around the error messages?
it seems you are not including the jesd204 ip from xlnx. you need that to compile
Thank you for your prompt reply.
The project sources indicates that the Jesd204 has been automatically added to the project:
I am wondering if I miss any step. Please kindly advise.
After updating the three IP cores, we have been able to synthesize the sample code but run into the three error messages during implementation (generating the Bitstream). The two screenshots below show the error messages.
Could you please let me know how to work around the error messages?