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Questions about the error “Timed out while attempting to fill FIFO (s)”

I tried to observe the FFT using the canvas [AD9680 FFT] setting in the VisualAnalog software, but the Graph-AD9680 FFT remains blank.
The message “ADC Data Capture: Error: Timed out while attempting to fill FIFO(s).” is displayed.
The AD9860-500EBZ evaluation board  and ADS7-V2EBZ data capture kit are used as equipment.
How can I get an FFT?
I made the following settings.
Set based on canvas ”AD9680 FFT”.
  •  The Device tab
      Capture: ADS7V2(00BE4DCA353BE4A)
      Device: AD9680
      Clock Frequency (MHz) : [1000]
      Output Data :Data[Ch.A Data]  Length[131072]
  •  The Capture Board tab
      The FPGA file uses the bin file “ad9680_ads7v2.bin”.
  •  The Device tab
      "Enable Data Capture Controrls" and "SPI Clock Rate :Slow" are set.
SPIContoroller software is also used.
Also describes the settings for it.
 The files “AD9680_14bit1.25GSspiR2Si.cfg” and “” were used.
  •  The Global tab
      “HEX 00000000 W 00000081 ADCO @ CSB1” was written to “GENERIC READ / WRITE”.
      In DEVICE INDEX (8), only “A” was set.
  • The ADCBase3 tab
      JESD 204B QUICK CONFIGURATION REG (570) was set as follows.

        Number of Lanes :4
        Number of Converters :2
        Number of Octets/Frame :1
  •     When PLL STATUS REG (56F) is read, [1] is displayed.
  • The ADCBase0 tab
      When CLOCK STATS REG(11C) is read, Clock detection status [Input clock detected] is displayed.

The following signals were connected to AD9860-500EBZ.

  •  Sample Clock: Connect a signal of 1GHz and amplitude of 14dBm to connector J801.
  •  Reference Clock: Connect a signal of 1GHz and amplitude of 10dBm to connector J804.
  •  Channel A: Connect the input signal generator to connector P200 using RG-58, 50Ω coaxial cable.
  •  Channel B: Connector P202 is not connected.

Since the "515 FPGA_DONE" LED of ADS7-V2EBZ is lit, configuration is complete.
The device manager of PC (Windows 7) recognizes ADS7-V2EBZ.

Thank you and best regards.