AD9822 output code

Hi Pavithra Joshi,

I moved your thread to the High-speed ADCs community. Someone here will be able to assist you.

Best regards,

Mark

Thanks Mark

Can you capture the waveform directly at the VINR pin to confirm it matches the op-amp output, other than having a different DC offset from the AD9822 clamp circuit.

Also, what are the units for the Y-axis of the "Output Voltage" plot- is this digital code converted back to volts?

When i probe at the VINR input pin, the CCD waveform is 2Vpkpk as such the OPAMP output, but with different DC offset. Since the clamp voltage is programmed to 3V using the configuration register, ecxpected  DC level is  3V, but actually it is 1.5V. 

I probed the offset pin to check the clamp voltage actually set and confirmed that it is 3V as programmed. 

I want to know why the clamped waveform cannot be seen in the VINR pin.

Also when i sweep the data level across 16384 levels with step  size of the ADC, the output code is always the first data level code.

The output codes are expected to also sweep as such the input which is swept across voltages.

Hi Barnes,

I need an immediate help on AD9822. I am facing an issue with the OFFSET pin.

I read through the posts of AD9826 in which there was a problem with the OFFSET pin.

I too observe that the OFFSET pin is decreasing to 0V and the input pin VINR is not clamping to the expected level.

I confirmed that the clocks are also continuous and following the same decaps as suggested in the application information.

Also i found that when DRVDD is 3V, with the input signal and the clocks are running, the OFFSET pin is constant at 3V but the input signal at VINR pin is not clamping to 3V(Programmed clamp voltage).

When DRVDD is 5V, with the input signal and the clocks are running, the OFFSET pin decreased to 0V and the input signal at VINR pin is not clamping to 3V(Programmed clamp voltage).

What is happening internally when DRVDD is operated at 3V and 5V? How the change is DRVDD is affecting the voltage at OFFSET pin when the AVDD is used for the potential divider to set the Clamp voltage?

Can you help me with this issue.

Thanks

Pavithra Joshi

The clamp circuit will charge the input capacitor and level shift your input signal, however the DC level shift will depend on the input signal level during the CDSCLK1 pulse. If you ground the op-amp side of the input capacitor, you should see the VINR pin stabilizing close to the clamp (OFFSET) voltage. Once the input signal is switching levels, you might see the average DC level be at a somewhat different level.

Regarding the DRVDD voltage dependence, this is not expected. The DRVDD supply only sets the digital output driver level, it should not be affecting the clamp/offset levels. Is it possible there is some connection on the PCB which is causing this? Did you confirm the digital output levels are matching the DRVDD voltage just as a basic test?

Hi Barnes,

Thanks for replying and helping me.

I verified the digital levels are at the DRVDD voltage.

I find the output of my code drop to random 0V. My input signal is CCD signal with reference to data level as 1V. 

Below is the waveform captured at VINR input(Yellow), CDSCLK1(Blue), CDSCLK2(Purple), ADCCLK(Green).In this below image the input signal did not clamp to 3V. But even though it clamps to 3V, i observe the dips to 0V.

But my output code is dropping to 0V randomly.Below is the plot with Output code (converted to volts) vs Number of samples captured.

Help me to solve this drooping issue which is occurring randomly for all the reference to data level voltages.

Below shown is the image of my bench setup.

Thanks

Pavithra Joshi