I am working with ad9655 now. I wonder where to find some simple FPGA source code of HSC-ADC-EVALCZ High speed for AD9655? Can some one help me?
You are very welcome. I hope your project goes well.
I emailed you some sample FPGA code for AD9655 capture on HSC-ADC-EVALCZ.
I hope your project goes well.
can you also send me sample FPGA code for HSC-ADC-EVALCZ? My project is using Xilinx Zynq to interface AD9655, and using similar FPGA IOs as used in Virtex 4 of HSC-ADC-EVALCZ
Thanks for your interest in AD9655. I'll request the code for you. Hopefully you'll receive it in a day or two.
thanks for your quick response and I had got the code.
unfortunately I got some new issue, after checking the code, that the code for virtex4(which use IDDR primitive) in HSC-ADC-EVALCZ is much different from suggested code in Xilinx 7 series FPGA(which support ISERDESE2 primitive)
do you have sample code of AD9655 with Xilinx 7 series FPGA?
I'm sorry but the only FPGA capture example we have for AD9655 is with Virtex 4.
I checked the FPGA developer and we do not use ISERDESE2 for any of our ADC capture solutions, so I cannot provide any example which uses ISERDESE2.
I'm sorry about that. Maybe you can get some information from Xilinx or one of their forums.
Please take care.
thank you very much for your clear result