I am wondering what “J6 ready signal” really represents on AD9694/ADS7-V2EBZ. I have measured the SMA GPIO J6 output signal on ADS7-V2EBZ. Even though AD9694 Eval board is enabled for the REFCLK (without the “External Trigger”) through Visual Analog and set the 1 GHz Clock and the 500 MHz sampling frequency through ACE , the J6 output signal is pulses with 1.6s repetition and 1.6ms pulse width:
The AD9695 External Trigger Quick Start Guide says, “the FPGA will send an output signal on SMA2 J6 when the FPGA is ready for another capture.”
Since 500 MHz signal fed to the SMA GPIO J3 (CLC) and no External Trigger is set, the ADS7 J6 output signal pulse repetition, “ready signal”, should be in the range of ns (for our example 2ns), but not 1.6s. Could you please elaborate on the ADS7-V2EBZ J6 output signal and let me know why the ADS7 J6 output pulse has the 1.6s repetition?